| Title: | 積體電路與電子系統之靜電放電防護技術產學聯盟( I ) Consortium of ESD Protection Technology for Circuits and Systems( I ) |
| Authors: | 柯明道 KER MING-DOU 國立交通大學電子工程學系及電子研究所 |
| Issue Date: | 2014 |
| Gov't Doc #: | MOST103-2622-E009-006 |
| URI: | http://hdl.handle.net/11536/98144 https://www.grb.gov.tw/search/planDetail?id=8209327&docId=435560 |
| Appears in Collections: | Research Plans |
- 積體電路與電子系統之靜電放電防護技術產學聯盟( II ) /
- 積體電路與電子系統之靜電放電防護技術產學聯盟( III ) / 柯明道
- Design on ESD protection scheme for IC with power-down-mode operation / Ker, MD;Lin, KH
- ESD (Electrostatic Discharge) protection design for nanoelectronics in CMOS technology / Ker, Ming-Dou
- Area-Efficient ESD-Transient Detection Circuit With Smaller Capacitance for On-Chip Power-Rail ESD Protection in CMOS ICs / Chen, Shih-Hung;Ker, Ming-Dou
- Overview on ESD Protection Designs of Low-Parasitic Capacitance for RF ICs in CMOS Technologies / Ker, Ming-Dou;Lin, Chun-Yu;Hsiao, Yuan-Wen
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