| Title: | 次世代智慧室內無線五十億級位元傳輸率之基頻傳收機技術應用與隨機運算IP-子計畫六：適用於室內五十億級位元傳輸率應用之具可變長度延遲資料路徑的高效能隨機ASIP處理器設計(2/3) Stochastic ASIP Processor with Variable-Latency Datapath for Next Generation Intelligent Wireless Indoor Multi-Gbps Applications |
| Authors: | 劉志尉 Liu Chih-Wei 國立交通大學電子工程學系及電子研究所 |
| Issue Date: | 2012 |
| Gov't Doc #: | NSC101-2220-E009-029 |
| URI: | http://hdl.handle.net/11536/98568 https://www.grb.gov.tw/search/planDetail?id=2548026&docId=387423 |
| Appears in Collections: | Research Plans |
