高階助聽器晶片及系統-子計畫四：助聽器數位積體電路設計( II )

Title:	高階助聽器晶片及系統-子計畫四：助聽器數位積體電路設計( II ) Digital Integrated Circuit Design for Hearing Aids
Authors:	劉志尉 Liu Chih-Wei 國立交通大學電子工程學系及電子研究所
Keywords:	雙耳助聽器;低功率低電壓數位電路;變動電路延遲資料路徑;適應性動態電壓調整;Binaural hearing aids;Low-power-low-voltage digital circuit;Variable-latency datapath;Adaptive voltage scaling
Issue Date:	2011
Gov't Doc #:	NSC100-2220-E009-005
URI:	http://hdl.handle.net/11536/99638 https://www.grb.gov.tw/search/planDetail?id=2364872&docId=374608
Appears in Collections:	Research Plans