標題: Technology mapping for FPGAs with composite logic block architectures
作者: Chuang, HH
Shung, CB
交大名義發表
電子工程學系及電子研究所
National Chiao Tung University
Department of Electronics Engineering and Institute of Electronics
關鍵字: technology mapping;FPGA;subject graph;pattern graph
公開日期: 1-十月-1996
摘要: A new technology mapping algorithm is developed on a general model of FPGA with composite logic block architectures consisting of different sizes of look-up tables (LUTs) and possibly different logic gates. In additions, the logic blocks may have hard-wired connections and limit accessible fanouts. Xilinx XC4000 is one one example containing LUTs of different sizes and AT&T ORCA is another example containing both LUTs and logic gates. We use a multiple-fanout pattern graph library to model the composite logic block and a premapping technique to generate the subject graph dynamically. A new matching algorithm and a new covering algorithm are also developed for the subject graph covering. The experimental results show that our algorithm is an effective technology mapper for FPGAs with composite logic block architectures, especially for large circuits. Over a set of MCNC benchmarks, our algorithm requires on the average 4.25% few CLBs than PPR, 6.79% fewer CLBs than TEMPT, and 2.79% fewer CLBs than ASYL when used as the XC4000 mapper. Over a set of larger benchmarks, our algorithm outperforms PPR by 13.70%. Very encouraging results were obtained when our algorithm is used as an ORCA mapper, while there was no prior published results.
URI: http://hdl.handle.net/11536/1017
ISSN: 0916-8532
期刊: IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS
Volume: E79D
Issue: 10
起始頁: 1396
結束頁: 1404
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