標題: | A low power turbo/Viterbi decoder for 3GPP2 applications |
作者: | Lin, CC Shih, YH Chang, HC Lee, CY 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
關鍵字: | cache memories;error correction;mobile communication;turbo;Viterbi decoding |
公開日期: | 1-四月-2006 |
摘要: | This paper presents a channel decoder that completes both turbo and Viterbi decodings, which are pervasive in many wireless communication systems, especially those that require very low signal-to-noise ratios. The trellis decoding algorithm merges them with less redundancy. However, the implementation is still challenging due to the power consumption in wearable devices. This research investigates an optimized memory scheme and rescheduled data flow to reduce power consumption and chip area. The memory access is reduced by buffering the input symbols, and the area is reduced by reducing the embedded interleaver memory. A test chip is fabricated in a 1.8 V 0.18-mu m standard CMOS technology and verified to provide 4.25-Mb/s turbo decoding and 5.26-Mb/s Viterbi decoding. The measured power dissipation is 83 mW, while decoding a 3.1 Mb/s turbo encoded data stream with six iterations for each block. The power consumption in Viterbi decoding is 25.1 mW in the 1-Mb/s data rate. The measurement shows the power dissipation is 83 mW for the turbo decoding with six iterations at 3.1 Mb/s, and 25.1 mW for the Viterbi decoding at 1 Mb/s. |
URI: | http://dx.doi.org/10.1109/TVLSI.2006.874375 http://hdl.handle.net/11536/12466 |
ISSN: | 1063-8210 |
DOI: | 10.1109/TVLSI.2006.874375 |
期刊: | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS |
Volume: | 14 |
Issue: | 4 |
起始頁: | 426 |
結束頁: | 430 |
顯示於類別: | 期刊論文 |