標題: | An 8 Gbps, 4:1 Transition-Aware Self-Toggling Multiplexer |
作者: | Chen, Wei-Zen Yang, Yi-Hung 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
關鍵字: | multiplexer;TSPC;dynamic flip flop;clock gating |
公開日期: | 1-一月-2014 |
摘要: | A novel 8Gbps, 4:1 transition aware multiplexer (MUX) is proposed. The multiplexer core is basically a self-toggling TSPC flip-flop, which is deactivated when no data transition is detected. The high speed serial data is regenerated by gating the triggered clock. It combines the advantages of data retiming to eliminate deterministic jitter. Besides, the short clock-to-Q(b) delay enables high speed multiplexing. Power reduction can be achieved by deactivating the power hungry flip-flop thanks to the random probability of data transition. Fabricated in 55 nm CMOS technology, the core circuit occupies a chip area of 77 x 81 mu m(2) only. It dissipates 10.3 mW from a 1.2 V supply. |
URI: | http://hdl.handle.net/11536/128602 |
ISBN: | 978-1-4799-5230-4 |
ISSN: | |
期刊: | 2014 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS) |
起始頁: | 659 |
結束頁: | 662 |
顯示於類別: | 會議論文 |