標題: | A standard cell-based frequency synthesizer with dynamic frequency counting |
作者: | Chen, PL Lee, CY 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
關鍵字: | frequency synthesizer;dynamic frequency counting (DFC);digitally-controlled varactors (DCV);digitally-con trolled oscillator (DCO);dynamic element matching (DEM);phase locked loop (PLL) |
公開日期: | 1-十二月-2005 |
摘要: | This paper presents a standard cell-based frequency synthesizer with dynamic frequency counting (DFC) for multiplying input reference frequency by N times. The dynamic frequency counting loop uses variable time period to estimate and tune the frequency of digitally-controlled oscillator (DCO) which enhances frequency detection's resolution and loop stability. Two ripple counters serve as frequency estimator. Conventional phase-frequency detector (PFD) thus is replaced with a digital arithmetic comparator to yield a divider-free circuit structure. Additionally, a 15 bits DCO with the least significant bit (LSB) resolution 1.55 ps is designed by using the gate capacitance difference of 2-input NOR gate in fine-tuning stage. A modified incremental data weighted averaging (IDWA) circuit is also designed to achieve improved linearity of DCO by dynamic element matching (DEM) skill. Based on the proposed standard cell-based frequency synthesizer, a test chip is designed and verified on 0.35-mu m complementary metal oxide silicon (CMOS) process, and has a frequency range of (18-214) MHz at 3.3 V with peak-to-peak (P-k-P-k)jitter of less than 70 ps at 192 MHz/3.3 V. |
URI: | http://dx.doi.org/10.1093/ietfec/e88-a.12.3554 http://hdl.handle.net/11536/13030 |
ISSN: | 0916-8508 |
DOI: | 10.1093/ietfec/e88-a.12.3554 |
期刊: | IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES |
Volume: | E88A |
Issue: | 12 |
起始頁: | 3554 |
結束頁: | 3563 |
顯示於類別: | 會議論文 |