標題: A High-Parallelism Memory-Based FFT Processor with High SQNR and Novel Addressing Scheme
作者: Huang, Shen-Jui
Chen, Sau-Gee
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: FFT;SQNR;Radix-4(2)
公開日期: 2016
摘要: This paper presents an area-efficient memory-based FFT processor for long FFT lengths. To achieve high throughput, radix-4(2) FFT algorithm is adopted to reduce number of FFT stages. For low-complexity realization of the main butterfly processing element, a folded-by-2 scheme along with an optimized scheduling is designed. Variable FFT lengths (i.e., 1024 similar to 32768 points) can be supported through flexible switch configurations. Moreover, a conflict-free memory addressing scheme is devised to support 16-way parallel and normal-order data input/output without re-ordering buffers. An optimized block floating-point (BFP) scheme is employed for long-length FFT operations. The EDA synthesis results with TSMC-90nm process show that the area of proposed FFT processor is 2.98 mm(2), and the power consumption is 29 mW @160MHz clock frequency. The SQNR performance is over 70dB for all supported FFT lengths with 16-bit wordlength.
URI: http://hdl.handle.net/11536/134375
ISBN: 978-1-4799-5341-7
ISSN: 0271-4302
期刊: 2016 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)
起始頁: 2671
結束頁: 2674
顯示於類別:會議論文