Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Chiu, Yu-Chien | en_US |
dc.contributor.author | Chang, Chun-Yen | en_US |
dc.contributor.author | Hsu, Hsiao-Hsuan | en_US |
dc.contributor.author | Cheng, Chun-Hu | en_US |
dc.contributor.author | Lee, Min-Hung | en_US |
dc.date.accessioned | 2017-04-21T06:49:01Z | - |
dc.date.available | 2017-04-21T06:49:01Z | - |
dc.date.issued | 2015 | en_US |
dc.identifier.isbn | 978-1-4673-7362-3 | en_US |
dc.identifier.issn | 1541-7026 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/134590 | - |
dc.description.abstract | We demonstrate a novel hybrid nonvolatile memory integrated with a charge trapping mechanism and a ferroelectric polarization effect. The hybrid memory features a large threshold voltage window of 2V, fast 20-ns program/erase time, tight switching margin, and long 10(12)-cycling endurance at 85 degrees C. Such excellent endurance reliability at 85 degrees C can be ascribed to the introduction of charge-trapping node into the design of memory structure that not only weakens temperature-dependent polarization relaxation, but also improves high-temperature endurance reliability. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | nonvolatile memory | en_US |
dc.subject | ferroelectric polarization | en_US |
dc.subject | charge trapping | en_US |
dc.subject | endurance | en_US |
dc.subject | retention | en_US |
dc.title | Impact of Nanoscale Polarization Relaxation on Endurance Reliability of One-Transistor Hybrid Memory Using Combined Storage Mechanisms | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2015 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS) | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000371888900150 | en_US |
dc.citation.woscount | 0 | en_US |
Appears in Collections: | Conferences Paper |