A 2 x 20-Gb/s, 1.2-pJ/bit, Time-Interleaved Optical Receiver in 40-nm CMOS

Abstract

This paper describes a single-chip, 2 x 20-Gb/s time-interleaved integrating-type optical receiver. Combining with correlation-based timing recovery and 1: 4 demultiplexer, it achieves a high energy efficiency of 1.2-pJ/bit. By incorporating the proposed alternating photodetector (ALPD) current-sensing scheme, the front-end receiver is 4-way time-interleaved to increase input sensitivity and relax operating speed of digital comparator. The optical receiver achieves an input sensitivity of 44 mu A(pp) at bit-error-rate of less than 10(-12). Fabricated in a 40-nm bulk CMOS technology, the chip size is 0.46 mm(2).