標題: A Low-Power Radix-4 Viterbi Decoder Based on DCVSPG Pulsed Latch with Sharing Technique
作者: Lee, Xin-Ru
Chang, Hsie-Chia
Lee, Chen-Yi
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: pulsed latch;DCVSPG;Viterbi decoder
公開日期: 2010
摘要: With a Viterbi decoder, the bit error probability of a communication system can be reduced. However, the power consumption of exploiting Viterbi decoder is an overhead to systems. In the Viterbi decoder, the survivor memory unit (SMU) is the most power critical due to data exchanging. A low-power radix-4 Viterbi decoder based on a differential cascode voltage switch with pass gate (DCVSPG) pulsed latch with sharing technique is proposed to process two bits concurrently. The dynamic power of SMU is reduced by the sharing technique. Moreover, the smaller clock loading also leads to power-efficient characteristic. Based on UMC 90nm process, the simulation results show the proposed Viterbi decoder with sharing technique could achieve better power scheme with energy efficiency 0.128 nJ/bit at 0.9V.
URI: http://hdl.handle.net/11536/14612
ISBN: 978-1-4244-7456-1
期刊: PROCEEDINGS OF THE 2010 IEEE ASIA PACIFIC CONFERENCE ON CIRCUIT AND SYSTEM (APCCAS)
起始頁: 1203
結束頁: 1206
顯示於類別:會議論文