標題: | A 7.72 Gb/s LDPC-CC Decoder with Overlapped Architecture for Pre-5G Wireless Communications |
作者: | Lin, Chia-Lung Liu, Rong-Jie Chen, Chih-Lung Chang, Hsie-Chia Lee, Chen-Yi 電機學院 電子工程學系及電子研究所 College of Electrical and Computer Engineering Department of Electronics Engineering and Institute of Electronics |
關鍵字: | LDPC convolutional codes;high throughput;LDPC;overlapped architecture;digital signal |
公開日期: | 1-一月-2016 |
摘要: | LDPC block codes (LDPC-BCs) have attracted great interests in recent years by highly parallel computation and good bit-error-rate performance, and one of the decoder implementation issues is high routing complexity. LDPC convolutional codes (LDPC-CCs) not only release routing complexity but also are natural to dynamic length of data frame. Thus, the codes are very suitable for video stream and pre-5G wireless communication systems. LDPC-CC decoder is composed of several concatenated processors, where the long FIFOs are usually the bottleneck of area and decoding latency. To improve hardware efficiency, we use overlapped architecture to share partial FIFO between processors. Furthermore, check node unit and hybrid-partitioned FIFO are proposed to increase throughput and pipeline efficiency. The measurement results of test chip in 65nm technology show that our work can achieves 7.72 Gb/s under 322MHz operating frequency. The decoder with 6 processors occupies an area of 1.19 mm(2), drawing 410.5 mW of power with an energy efficiency of 8.75pJ/bit/proc. |
URI: | http://hdl.handle.net/11536/146560 |
期刊: | 2016 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC) |
起始頁: | 337 |
結束頁: | 340 |
顯示於類別: | 會議論文 |