標題: Cellular Automata Based Hardware Accelerator for Parallel Maze Routing
作者: Saurabh, Shashank
Lin, Kuen-Wey
Li, Yih-Lang
資訊工程學系
Department of Computer Science
關鍵字: maze routing;hardware accelerator;cellular automata
公開日期: 1-一月-2016
摘要: This paper introduces a scalable hardware design to accelerate the maze algorithm for VLSI routing on Cellular automata (CA). The time-complexities of wave-propagation and back-tracing on CA are both O(n) while constant time for label clearing. Innately high parallelism of CA largely reduces the runtime in wave propagation and label clearing. The RTL implementation for this design has been developed in Verilog and a cell lattice of 35. 35 cells has been implemented on FPGA. The runtime of the proposed CA is shorter than that on a sequential computer by about four to five orders of magnitude.
URI: http://hdl.handle.net/11536/146579
期刊: PROCEEDINGS OF THE IEEE INTERNATIONAL CONFERENCE ON ADVANCED MATERIALS FOR SCIENCE AND ENGINEERING (IEEE-ICAMSE 2016)
起始頁: 680
結束頁: 683
顯示於類別:會議論文