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dc.contributor.authorKer, Ming-Douen_US
dc.contributor.authorWang, Chang-Tzuen_US
dc.date.accessioned2014-12-08T15:24:42Z-
dc.date.available2014-12-08T15:24:42Z-
dc.date.issued2009en_US
dc.identifier.isbn978-1-4244-4072-6en_US
dc.identifier.urihttp://hdl.handle.net/11536/17140-
dc.description.abstractElectrostatic discharge (ESD) protection for mixed-voltage I/O interfaces has been one of the major challenges of system-on-a-chip (SOC) implementation in nanoscale CMOS processes. Moreover, the gate leakage current across thin gate-oxide devices has serious degradation on circuit performance while circuits implementing in nanoscale CMOS processes. The on-chip ESD protection circuit for mixed-voltage I/O buffers should meet the gate-oxide reliability constraints and be designed with consideration of gate leakage current. This paper presents the effective ESD protection scheme with circuit solutions to protect the mixed-voltage I/O buffers in nanoscale CMOS processes against ESD stresses. The proposed ESD protection scheme and the specific ESD clamp circuits with low standby leakage current have been successfully verified in nanoscale CMOS processes. Effective on-chip ESD protection scheme should be early planed and started in the beginning phase of chip design in order to achieve good enough ESD robustness for IC products.en_US
dc.language.isoen_USen_US
dc.titleCircuit Solutions on ESD Protection Design for Mixed-Voltage I/O Buffers in Nanoscale CMOSen_US
dc.typeProceedings Paperen_US
dc.identifier.journalPROCEEDINGS OF THE IEEE 2009 CUSTOM INTEGRATED CIRCUITS CONFERENCEen_US
dc.citation.spage689en_US
dc.citation.epage696en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000275926300148-
Appears in Collections:Conferences Paper