標題: Memory system design in superscalar processing
作者: Lu, NP
Chung, CP
交大名義發表
資訊科學與工程研究所
National Chiao Tung University
Institute of Computer Science and Engineering
關鍵字: superscalar processing;load/store port;cache;memory consistency model
公開日期: 1-Sep-1995
摘要: In this paper, we study the memory system design for superscalar processing. Benchmarking is used to examine the execution behavior of load/store instructions, such as load/store parallelism and memory load/store port utilization. It is found that the use of only a single load/store port forms a system bottleneck. A superscalar processor benefits from multiple load/store ports and system performance saturates with two load/store ports. The memory system must be carefully designed if multiple load/store ports are supported in a superscalar processor. Thus, we consider the design of the data cache subsystem. The data cache configurations we investigate include multiported cache, multibank cache, and duplicated cache. Through benchmarking, we find that the duplicated cache performs well in most benchmarks. Yet the cost of a duplicated cache is higher. In a superscalar multiprocessing environment, in order to properly maintain memory consistency, we must consider the load/store ordering of the processors. In superscalar processors, the load/store ordering may be in one of three forms: total ordering, load bypassing, and load forwarding. In this research, we conclude that to support the sequential consistency model, the load/store instructions must be totally ordered. Load bypassing and load forwarding are sufficient to support the processor consistency model.
URI: http://dx.doi.org/10.1142/S0129053395000233
http://hdl.handle.net/11536/1758
ISSN: 0129-0533
DOI: 10.1142/S0129053395000233
期刊: INTERNATIONAL JOURNAL OF HIGH SPEED COMPUTING
Volume: 7
Issue: 3
起始頁: 421
結束頁: 443
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