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dc.contributor.authorPan, Po-Chengen_US
dc.contributor.authorChen, Hung-Mingen_US
dc.contributor.authorCheng, Yi-Kanen_US
dc.contributor.authorLiu, Jillen_US
dc.contributor.authorHu, Wei-Yien_US
dc.date.accessioned2014-12-08T15:30:08Z-
dc.date.available2014-12-08T15:30:08Z-
dc.date.issued2012en_US
dc.identifier.isbn978-1-4503-1573-9en_US
dc.identifier.urihttp://hdl.handle.net/11536/21596-
dc.description.abstractIn this paper, we present a novel configurable analog routing methodology for more efficient analog layout automation. By the help of OpenAccess constraint group format, the technology process rules and analog layout design intention/constraints are unified through schematic level to layout level. In contrast to self-defined constraint format in prior arts, proposed approach manipulates the analog routing characteristic based on the unified constraints. In different circuit hierarchies defined by circuit designers or extracted by existing placement, the hierarchical structure is formed as specific analog layout constraint groups. This work efficiently facilitates analog routing strategy which honors the specific analog constraints. By practicing on an analog functional block of tsmc 40nm SoC design which guarantees to be legalized and satisfies required analog constraints by DRC/LVS and post-layout simulation respectively, the results in wire matching for signal integrity show that the different routing priority generated by our approach can have significant performance impact.en_US
dc.language.isoen_USen_US
dc.titleConfigurable Analog Routing Methodology via Technology and Design Constraint Unificationen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2012 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD)en_US
dc.citation.spage620en_US
dc.citation.epage626en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000317001300100-
Appears in Collections:Conferences Paper