標題: | A 3.66Gb/s 275mW TB-LDPC-CC Decoder Chip for MIMO Broadcasting Communications |
作者: | Chen, Chih-Lung Lan, Yu-Cheng Chang, Hsie-Chia Lee, Chen-Yi 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
關鍵字: | LDPC-CC;tail-biting;high throughput |
公開日期: | 2013 |
摘要: | In this work, a decoder chip for time-invariant tail-biting LDPC convolutional code (TB-LDPC-CC) is proposed. By modifying the layered decoding scheduling, the proposed decoding algorithm can achieve twice faster decoding convergence than the conventional flooding scheduling. Furthermore, 30.77% storage requirement is also reduced due to adaptive channel value addressing employed in memory-based decoder design. The multiple frame sizes handling ability can lower the power and adapt to multiple applications. By integrating these techniques, a TB-LDPC-CC decoder chip supporting three frame sizes is implemented in UMC 90nm CMOS technology. The decoder containing 4 processors occupies 2.18mm(2) area and provides maximum throughput 3.66Gb/s under 0.8V supply and 305MHz with a 18.8pJ/bit/proc energy efficiency. |
URI: | http://hdl.handle.net/11536/23719 |
ISBN: | 978-1-4799-0277-4978-1-4799-0280-4 |
期刊: | PROCEEDINGS OF THE 2013 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC) |
起始頁: | 153 |
結束頁: | 156 |
顯示於類別: | 會議論文 |