標題: | An IP synthesizer for limited-resource DWT processor |
作者: | Dung, LR 電控工程研究所 Institute of Electrical and Control Engineering |
關鍵字: | discrete wavelet transform;VLSI;silicon intelligent property;DSP;computer architecture |
公開日期: | 1-十二月-2004 |
摘要: | This paper presents a VLSI design methodology for the MAC-level DWT/IDWT processor based on a novel limited-resource scheduling algorithm. The r-split Fully-specified Signal Flow Graph (FSFG) of limited-resource FIR filtering has been developed for the scheduling of the MAC-level DWT/IDWT signal processing. Given a set of architecture constraints and DWT parameters, the scheduling algorithm can generate four scheduling matrices that drive the data path to perform the DWT computation. Because the memory for the inter-octave is considered with the register of FIR filter, the memory size is less than the traditional architecture. Besides, based on the limited-resource scheduling algorithm, an automated DWT processor synthesizer has been developed and generates constrained DWT processors in the form of silicon intelligent property (SIP). The DWT SIP can be embedded into a SOC or mapped to program codes for commercial off-the-shelf (COTS) DSP processors with programmable devices. As a result, it has been successfully proven that a variety of DWT SIPS can be efficiently realized by tuning the parameters and applied for signal processing applications. |
URI: | http://hdl.handle.net/11536/25608 |
ISSN: | 0916-8508 |
期刊: | IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES |
Volume: | E87A |
Issue: | 12 |
起始頁: | 3047 |
結束頁: | 3056 |
顯示於類別: | 期刊論文 |