標題: Crosstalk-driven interconnect optimization by simultaneous gate and wire sizing
作者: Jiang, IHR
Chang, YW
Jou, JY
資訊工程學系
電子工程學系及電子研究所
Department of Computer Science
Department of Electronics Engineering and Institute of Electronics
關鍵字: deep submicrometer;gate sizing;interconnect;performance optimization;physical design;routing
公開日期: 1-九月-2000
摘要: Noise, as well as area, delay, and power, is one of the most important concerns in the design of deep submicrometer integrated circuits. Currently existing algorithms do not handle simultaneous switching conditions of signals for noise minimization. In this paper, we model not only physical coupling capacitance, but also simultaneous switching behavior for noise optimization. Based on Lagrangian relaxation, we present an algorithm which ran optimally solve the simultaneous noise, area, delay, and power optimization problem by sizing circuit components. Our algorithm, with linear memory requirement and linear runtime, is very effective and efficient. For example, for a circuit of 6144 wires and 3512 gates, our algorithm solves the simultaneous optimization problem using only 2.1-MB memory and 19.4-min runtime to achieve the precision of within 1% error on a SUN Spare Ultra-I workstation.
URI: http://dx.doi.org/10.1109/43.863640
http://hdl.handle.net/11536/30285
ISSN: 0278-0070
DOI: 10.1109/43.863640
期刊: IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
Volume: 19
Issue: 9
起始頁: 999
結束頁: 1010
顯示於類別:期刊論文


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