標題: An Efficient LDPC Decoder Architecture with a High-Performance Decoding Algorithm
作者: Hung, Jui-Hui
Chen, Sau-Gee
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: channel coding;LDPC;decoder;algorithm;hardware
公開日期: 1-十一月-2010
摘要: In this work a high performance LDPC decoder architecture is presented It is a partially parallel architecture for low complexity consideration In order to eliminate the idling time and hardware complexity in conventional partially parallel decoders the decoding process decoder architecture and memory structure are optimized Particularly the parity check matrix is optimally partitioned into four unequal sub matrices that lead to high efficiency in hardware sharing As a result it can handle two different codewords simultaneously with 100% hard ware utilization Furthermore for minimizing the performance loss due to round off errors in fixed point implementations the well known mod died min sum decoding algorithm is enhanced by our recently proposed high performance CMVP decoding algorithm Overall the proposed de coder has high throughput low complexity and good BER performances In the circuit implementation example of the (576 288) parity check matrix for IEEE 802 16e standard the decoder achieves a data rate of 5 5 Gbps assuming 10 decoding iterations and 7 quantization bits with a small area of 653K gates based on UMC 90 nm process technology
URI: http://dx.doi.org/10.1587/transcom.E93.B.2980
http://hdl.handle.net/11536/31979
ISSN: 0916-8516
DOI: 10.1587/transcom.E93.B.2980
期刊: IEICE TRANSACTIONS ON COMMUNICATIONS
Volume: E93B
Issue: 11
起始頁: 2980
結束頁: 2989
顯示於類別:期刊論文


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