標題: Methods for Power/Throughput/Area Optimization of H.264/AVC Decoding
作者: Xu, Ke
Liu, Tsu-Ming
Guo, Jiun-In
Choy, Chiu-Sing
交大名義發表
National Chiao Tung University
關鍵字: ASIC;Cost;Decoding;H.264/AVC;Memory;Performance;Power
公開日期: 1-七月-2010
摘要: This paper presents methods for efficient optimization of ASIC implementation for H.264/AVC video decoding. A systematic approach in optimization is presented in a top-down flow. Tradeoffs among Power, Throughput, and Area (PTA) at both system level and block level are studied and balanced. The system architecture is first evaluated. We then focus on the pipeline organization, parallelism, and memory architecture optimization. Different pipeline granularities are compared and their pros-and-cons are evaluated. Various parallel scenarios, especially 1 x 4-column and 4 x 1-row, are analyzed and compared. Then the detailed designs of various building blocks, such as inverse transform, inter prediction, and deblocking filter, are evaluated and their intrinsic characteristics are exploited to facilitate PTA optimization. Finally, we provide the design guidelines for ASIC implementation based on the analysis and our design experiences of five dedicated decoder chips.
URI: http://dx.doi.org/10.1007/s11265-009-0408-6
http://hdl.handle.net/11536/5160
ISSN: 1939-8018
DOI: 10.1007/s11265-009-0408-6
期刊: JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY
Volume: 60
Issue: 1
起始頁: 131
結束頁: 145
顯示於類別:期刊論文


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