探討P 型 SONOS 快閃記憶體元件抹寫週期忍耐度 之研究

Abstract

本篇論文主要研究P型SONOS快閃記憶體元件抹寫週期的忍耐度(endurance)藉由電洞引發熱電子 (CHHIHE) 動態寫入機制 (dynamic programming) 和 福勒-諾德漢穿隧 (FN tunneling erase) 抹除機制。採用三維元件模擬，來驗證量測特性。我們發現週期忍耐度後臨限電壓位移，閘極引發汲極漏電流(GIDL current) 上升 和次臨界擺幅 (SS) 上升等現像發生。本論文主要討論三種模型，發現电子捕陷模型(electron trap model)和界面態階模型(interface state model) 為最可能週期忍耐度後發生退化的主要原因。

In this thesis, we investigate endurance characteristic for 10K cycles in P-channel silicon-oxide-nitride-oxide-silicon (SONOS) memory device by using dynamic programming (PGM) scheme of Channel Hot Hole Induced Hot Electron injection (CHHIHE) and Fowler-Nordheim tunneling (FN) erase. After endurance, the Vt shift, gate-induced drain leakage (GIDL) current increase and subthreshold swing (SS) degradation occurred. So, in this work, 3 possible models of degradation are investigated by examining the measurement data and found that the electron trap and interface state models are the most reasonable to affect these degradations.