具有奈米線通道的矽鍺及雙閘極薄膜電晶體特性分析

Abstract

在本篇論文中，我們製作了一種具有奈米通道的多晶矽和多晶矽鍺薄膜電晶體，並且分析其特性。因為奈米線通道為多晶的結構，為了更有效修補其中的缺陷及斷鍵，我們對元件使用了氨電漿的處理，讓通道中的缺陷得到修補，使元件有更好的操作特性，例如：降低漏電流、提升載子遷移率、增強開啟電流等。我們也分別分析並討論了有關矽和矽鍺薄膜電晶體的漏電機制。雖然二種電晶體的結構相同，但因為矽鍺通道中有較多的缺陷，造成主要影響漏電的區域不同，也因此有著不同的漏電機制。 在本實驗中，我們也製作了具有雙閘極奈米通道的多晶矽薄膜電晶體。雖然有著雙閘極的結構，但在製作過程中，並不需要添加額外的光罩步驟，就能在通道上額外加上副閘極。雙閘極操作為將主閘極和副閘極提供相同電壓，因為雙閘極對通道會有較好的操控能力，所以雙閘極操作會有較好的元件特性。此外，我們可以藉著提供不同的副閘極電壓，使臨界電壓隨之調變，且不論導通通道長短或是氨電漿處理時間長短，臨界電壓的調變都是接近線性的。此外，在實驗中也發現，副閘極可輔助主閘極使其在操作時對導通通道有更好的操作能力，並使DIBL的效應降低。

In this thesis, we fabricated a novel TFT with nanowire channels and analyzed its characteristics. In order to improve the device performance, we performed the NH3 plasma treatment to passivate defects, reduce leakage current, enhance carrier mobility, increase driving current and decrease subthreshold slope. We also analyzed and discussed the leakage mechanisms of TFTs with Si and SiGe channels. SiGe films are found to contain more traps and defects which lead to worse characteristics as compare with their poly-Si counterparts. In addition, the major leakage paths of the poly-SiGe devices are found to be different from those in the poly-Si ones. Moreover, a new poly-Si nanowire TFT structure equipped with a sub-gate is proposed and demonstrated. The fabrication of such double-gated structure does not require extra mask. When the main-gate and sub-gate are tied together, denoted as the double-gated mode, the TFT performance is improved. It is also shown that threshold voltage can be modulated by varying the sub-gate voltage, and the modulation in Vth shows linear dependence on the applied sub-gate bias regardless of channel length or plasma passivation time. The sub-gate can also reduce DIBL effect by assisting the main-gate in controlling the channel potential more efficiently.