Browsing by Author "CHANG, RI"
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Item type:Item, A FUZZY-NEURO APPROACH FOR TIMING-DRIVEN SYSTEM PARTITIONING IN VLSI MULTI-CHIP DESIGN(1994) ;CHANG, RI ;HSIAO, PY ;資訊工程學系Department of Computer ScienceItem type:Item, A NEURAL-BASED PLACEMENT TECHNIQUE FOR RECTILINEAR APPLICATION(1993) ;CHANG, RI ;CHANG, JC ;HSIAO, PY ;資訊工程學系Department of Computer ScienceItem type:Item, ARBITRARILY SHAPED CELL PLACEMENT BY 3-LAYER SELF-ORGANIZING NEURAL NETWORKS(1994) ;CHANG, RI ;HSIAO, PY ;資訊工程學系Department of Computer ScienceItem type:Item, ARTIFICIAL TEXTURE GENERATION USING FORCE DIRECTED SELF-ORGANIZING MAPS(1994) ;CHANG, RI ;HSIAO, PY ;資訊工程學系Department of Computer ScienceItem type:Item, CIRCUIT PLACEMENT IN ARBITRARILY-SHAPED REGIONS USING NEURAL-NETWORK(1993) ;CHANG, RI ;HSIAO, PY ;資訊工程學系Department of Computer ScienceItem type:Item, FORCE DIRECTED SELF-ORGANZING MAPS FOR L-SHAPED CELL PLACEMENT USING DELTA LEARNING RULE(1994) ;CHANG, RI ;HSIAO, PY ;資訊工程學系Department of Computer ScienceItem type:Item, GENETIC ALGORITHMS FOR THE MODULE ORIENTATION PROBLEM(1994-07-21) ;CHANG, RI ;HSIAO, PY ;交大名義發表 ;資訊工程學系National Chiao Tung UniversityTo solve the module orientation problem the optimal number of flips of modules needs to be determined so as to minimise total wire length. A genetic-based module orientation method is proposed. Experiments show that the proposed method performs better than the best method known for this problem.Item type:Item, RECTANGULAR VLSI CELL PLACEMENT USING FORCE DIRECTED SELF-ORGANIZING MAPS AND DELTA LEARNING RULES(1994) ;CHANG, RI ;HSIAO, PY ;資訊工程學系Department of Computer ScienceItem type:Item, SOLVING SYSTEM PARTITIONING PROBLEM USING A MASSIVELY-PARALLEL BIO-COMPUTING NETWORK(1994) ;CHANG, RI ;HSIAO, PY ;交大名義發表 ;資訊工程學系National Chiao Tung UniversityIn this paper a massively parallel bio-computing network model is presented for the system partitioning problem in VLSI CAD under timing and capacity constraints. Experiments show that the proposed method was able to find optimal solutions with fast feedback. The future research is to develop a neural network based CAD system for resolving time-consuming VLSI design problems.