Browsing by Author "CHANG Hsie-Chia"

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APPARATUS AND METHOD OF PROCESSING CYCLIC CODES
(2011-12-01)
LIN Yi-Min
;
YANG Chi-Heng
;
CHANG Hsie-Chia
;
LEE Chen-Yi
An apparatus and a method of processing cyclic codes are disclosed herein, where the apparatus includes at least one reconfigurable module and an encoder controller. The reconfigurable module includes a plurality of linear feedback shift registers. The encoder controller can control the reconfigurable module to factor a generator polynomial into a factorial polynomial. In the reconfigurable module, the linear feedback shift registers can register a plurality of factors of the factorial polynomial respectively.
ELECTRONIC DEVICE AND METHOD FOR PROTECTING AGAINST DIFFERENTIAL POWER ANALYSIS ATTACK
(2012-06-21)
LIU Po-Chun
;
CHANG Hsie-Chia
;
LEE Chen-Yi
An electronic device and a method for protecting against a differential power analysis attack are disclosed herein. The electronic device includes an encryption/decryption unit, a random number generator and a countermeasure circuit. The encryption/decryption unit can provide an enable signal when encrypting or decrypting more bits of data. The random number generator can generate random data. When receiving the enable signal, the countermeasure circuit can operate according to the bits of data and the random data.
FULLY PARALLEL ENCODING METHOD AND FULLY PARALLEL DECODING METHOD OF MEMORY SYSTEM
(2014-04-03)
CHU Chia-Ching
;
LIN Yi-Min
;
YANG Chi-Heng
;
CHANG Hsie-Chia
A memory system, a fully parallel encoding method, and a fully parallel decoding method are disclosed. The encoding method utilizes a plurality of minimal polynomials that constitute a generator polynomial to derive a plurality of roots from the minimal polynomials. A first encoding matrix derived according to the roots of the minimal polynomials is subsequently decomposed to derive a second encoding matrix, in which partial elements of the second encoding matrix are common in those of a parity check matrix of the decoder, such that the encoder and the decoder can efficiently share the same hardware. In addition, the decoding method defines a new error locator polynomial and utilizes a cubic matrix operation to respectively combine the equations, which reduces the hardware required by the fully parallel architecture.