Browsing by Author "CHEN, CC"

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A 1.5 v CMOS current-mode cyclic analog-to-digital converter with digital error correction
(1995)
CHEN, CC
;
WU, CY
;
CHO, JJ
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A CMOS TRANSISTOR-ONLY 8-B 4.5-MS/S PIPELINED ANALOG-TO-DIGITAL CONVERTER USING FULLY-DIFFERENTIAL CURRENT-MODE CIRCUIT TECHNIQUES
(1995-05-01)
WU, CY
;
CHEN, CC
;
CHO, JJ
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Fully-differential current-mode circuit techniques are developed for the design of a pipelined current-mode analog-to-digital converter (IADC) in the standard CMOS digital processes. In the proposed IADC, the 1-b-per-stage architecture based on the reference nonrestoring algorithm is adopted. Thus large component ratios can be avoided and the linearity errors caused by device mismatches can be minimized. As one of the key subcircuits in the IADC, an offset-canceled high speed differential current comparator (CCMP) is proposed and analyzed. In the CCMP, the subtractions of offsets are performed in the current domain without floating capacitors. Moreover, the other key subcircuit, the current sample-and-hold amplifier (CSHA), is also developed to realize the pipeline architecture. An experimental chip for the proposed IADC has been fabricated in 0.8-mu m n-well CMOS technology. Using a single 5-V power supply, the fabricated IADC can be operated at 4,5-Ms/s conversion rate with a signal-to-noise-and-distortion-ratio (SNDR) of 51 dB (effective 8.2-b) for the input signal at 453 kHz. For 8-b resolution, the fabricated IADC can be operated at 4,5-Ms/s conversion rate with both differential nonlinearity (DNL) and integral nonlinearity (INL) below +/-0.6 LSB. The power consumption and the active chip area are 16 mW/b and 0.73 mm(2)/b, respectively.
A STUDY OF STICK SLIP MOTION AND ITS INFLUENCE ON THE CUTTING PROCESS
(1993-05-01)
CHIN, JH
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CHEN, CC
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交大名義發表
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機械工程學系
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National Chiao Tung University
The stick slip motion of a machine tool has been investigated on the basis of a complete kinematic and kinetic model. The model is a generalized description of stick-slip motion of the machine tool which governs the whole cyclic process of this phenomenon and not just its slipping mode. Using this method some dynamic characteristics of this motion have been clarified. Further, an extended theory for chip-formation dynamics has been suggested to include the variation of feed. The effect of stick-slip motion has been introduced to examine the influence of this variation. Finally an identification technique has been presented to determine the stick-slip parameters of the model.
COMPACT EMBEDDING OF BINARY-TREES INTO HYPERCUBES
(1995-04-28)
CHEN, CC
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CHEN, RJ
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資訊工程學系
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Department of Computer Science
DIFLUOROSILYLENE AS A PRECURSOR FOR THE CHEMICAL VAPOR-DEPOSITION OF TITANIUM SILICIDE
(1992-09-01)
CHEN, CC
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YU, JL
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LEE, CY
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LIU, CS
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CHIU, HT
A new method for preparing thin films of titanium silicide, TiSi2, by chemical vapour deposition of difluorosilylene and titanium tetrachloride is reported.
HIGH-SPEED REED-SOLOMON DECODER FOR CORRECTING ERRORS AND ERASURES
(1993-08-01)
WEI, CH
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CHEN, CC
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LIU, GS
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電控工程研究所
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電信研究中心
A Reed-Solomon decoder for errors-and-erasures correction, based on a new algebraic decoding algorithm, is presented. This high-speed decoder requires only n clock cycles for decoding each received n-symbol block. A serial structure that requires very few multipliers and provides a general expression to calculate the coefficients of the erasure-locator polynomial is also presented. A (15, 11) RS decoder and its shortened version (7, 3) RS decoder are used as design examples to illustrate the operating procedure of the new decoding algorithm.
PRECISE CMOS CURRENT SAMPLE HOLD CIRCUITS USING DIFFERENTIAL CLOCK FEEDTHROUGH ATTENUATION TECHNIQUES
(1995-01-01)
WU, CY
;
CHEN, CC
;
CHO, JJ
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
New CMOS current sample/hold (CSH) circuits capable of overcoming the accuracy limitations in conventional circuits without significantly reducing operating speed are proposed and analyzed. A novel differential clock feedthrough attenuation (DCFA) technique is developed to attenuate the signal-dependent clock feedthrough errors. Unlike conventional techniques, the DCFA circuit allows the use of dynamic mirror techniques, and results in no additional finite output resistance errors or device mismatch errors. The test chip of the proposed fully differential CSH circuit with multiple outputs has been fabricated in 1.2-mu m CMOS technology. Using a single 5-V power supply, experimental results show that the signal-dependent clock feedthrough error current is less than +/-0.4 mu A for the input currents from -550 mu A to 550 mu A. The acquisition time for a 900-mu A step transition to 0.1% settling accuracy is 150 ns. For a 410-mu A(p-p) input at 250 kHz with the fabricated fully-differential CSH circuit clocked at 4 MHz, a total harmonic distortion of -60 dB, and a signal-to-noise ratio of 79 dB have been obtained. The active chip area and power consumption of the fabricated CSH circuit are 0.64 mm(2) and 20 mW, respectively. Both simulation and experimental results have successfully verified the functions and performance of the proposed CSH circuits.