Browsing by Author "CHEN, JE"

Now showing 1 - 8 of 8

ALGEBRAIC DIVISION FOR MULTILEVEL LOGIC SYNTHESIS OF MULTIVALUED LOGIC-CIRCUITS
(1994)
WANG, HM
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LEE, CL
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CHEN, JE
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
CIRCUIT EXAMPLE TO DEMONSTRATE THAT FAN-OUT STEMS OF PRIMARY INPUTS MUST BE CHECKPOINTS
(1989-12-07)
CHEN, JE
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LEE, CL
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SHEN, WZ
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交大名義發表
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電控工程研究所
COMPLETE TEST SET FOR MULTIPLE-VALUED LOGIC-NETWORKS
(1994)
WANG, HM
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LEE, CL
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CHEN, JE
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
DISTRIBUTED FAULT SIMULATION FOR SEQUENTIAL-CIRCUITS BY PATTERN PARTITIONING
(1995-07-01)
WU, WC
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LEE, CL
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CHEN, JE
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LIN, WY
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電子工程學系及電子研究所
The paper investigates distributed fault simulation by pattern partitioning for sequential circuits. Simulation is done by making each distributed machine perform fault-free simulation with preceding patterns and then perform fault simulation with its own patterns. The fault simulation is accelerated since the number of patterns needed to be performed fault simulation for each machine is reduced by a factor of n, the number of machines, and the faults detected by any machine are dropped through communication of the network. A superlinear speedup can be obtained because this method can automatically remove the Case 1 faults, which are time consuming faults and would be considered to be undetected in the traditional three-valued fault simulation but are in fact truly detected. A mathematical model is also presented to predict the performance of the distributed fault simulation.
FAULT ANALYSIS ON (K+1)-VALUED PLA STRUCTURE LOGIC-CIRCUITS
(1993-06-01)
WANG, HM
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LEE, CL
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CHEN, JE
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交大名義發表
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電子物理學系
This paper presents a general form and a set of basic gates to implement (K+1)-valued PLA structure logic circuits. A complete fault analysis on the proposed circuit has been done and it is shown that all fanout stem faults can be collapsed to branch faults. A procedure for fault collapsing is derived. For any function implemented in the (K+1)-valued circuit, the number of remaining faults is smaller than that of the 2-valued circuit after the collapsing, where the value of K is dependent on the number of outputs and the assignment of the OR plane of the 2-valued logic circuit.
IDENTIFYING UNTESTABLE FAULTS IN SEQUENTIAL-CIRCUITS
(1995-09-01)
LIANG, HC
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LEE, CL
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CHEN, JE
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This article proposes an efficient method to identify untestable faults in sequential circuits. It uses a controllability calculation and symbolic simulation procedure that propagates the characteristics of unknown initial flip-flop states throughout the circuit. Identifying flip-flops that cannot be initialized and circuit lines that cannot be justified to definite values, this process classifies and identifies four types of untestable faults. Experimental results show that it improves the efficiency of a test generation system.
MY-BOX REPRESENTATION FOR FAULTY CMOS CIRCUITS
(1990-06-01)
CHEN, JE
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LEE, CL
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SHEN, WZ
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交大名義發表
;
電控工程研究所
SINGLE-FAULT FAULT-COLLAPSING ANALYSIS IN SEQUENTIAL LOGIC-CIRCUITS
(1991-12-01)
CHEN, JE
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LEE, CL
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SHEN, WZ
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper studies single-fault fault collapsing in sequential logic circuits. Two major phenomena, self-hiding (SH) and delayed reconvergence (DR), which arise from the existence of feedback paths and storage elements in sequential circuits, are analyzed and found to cause the dominance relationship which is valid in combinational circuits but no longer valid in sequential circuits. A fault-collapsing procedure is proposed to collapse faults in sequential circuits. It first collapses faults in the non-SAD (self-hiding and delayed-reconvergence) gates of the combinational part of the sequential circuit and then further collapses faults by identifying the prime fan-out branches. Finally, it collapses faults in feedback lines. The collapsed faults constitute a sufficient representative set of prime faults. This procedure has been applied to collapse faults for 31 benchmark sequential circuits [1] and the number of faults has collapsed to 43% of the original number.