Browsing by Author "CHEN, LP"

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ABRUPTNESS OF GE COMPOSITION AT THE SI/SIGE INTERFACE GROWN BY ULTRAHIGH-VACUUM CHEMICAL-VAPOR-DEPOSITION
(1995-08-21)
TSAI, WC
;
CHANG, CY
;
JUNG, TG
;
LIOU, TS
;
HUANG, GW
A model is proposed to estimate the interfacial abruptness of the Si/SiGe heterojunction. In this model, a transition region with linearly graded Ge composition is assumed at the Si/SiGe interface. The Ge composition x of Si/SiGe quantum well grown by ultrahigh vacuum chemical vapor deposition at 550 degrees C is found to increase with the deposition time as deposition at the same gas phase composition. This phenomenon can be explained by this model and the fitting results match the measured data. The thickness of the transition region and the transition time can be extracted from these fittings. The transition thicknesses are found to be about 1.9 nm or thinner as grown at 550 degrees C or below. (C) 1995 American Institute of Physics.
BORON INCORPORATION IN SI1-XGEX FILMS GROWN BY ULTRAHIGH-VACUUM CHEMICAL-VAPOR-DEPOSITION USING SI2H6 AND GEH4
(1995-11-13)
CHEN, LP
;
CHOU, CT
;
HUANG, GW
;
TSAI, WC
;
CHANG, CY
0.1% B2H6 diluted in hydrogen is used as the p-type dopant gas in Si1-xGex grown by ultrahigh vacuum chemical vapor deposition (UHVCVD) using Si2H6 and GeH4. The boron concentration is evaluated by secondary ion mass spectrometry (SIMS). The boron concentration of Si1-xGex increases with the increase of the GeH4 flow rate, that is, Ge fraction, by keeping Si2H6 and B2H6 how rates constant. The result may be due to the increase of the vacant surface sites which is caused by the increase of the hydrogen desorption rate when a higher Ge fraction epilayer is grown. (C) 1995 American Institute of Physics.
CHARACTERIZATION OF THE SI/SIGE HETEROJUNCTION DIODE GROWN BY ULTRAHIGH-VACUUM CHEMICAL-VAPOR-DEPOSITION
(1994-10-15)
JUNG, TG
;
CHANG, CY
;
LIU, CS
;
CHANG, TC
;
LIN, HC
The unipolar Si/SiGe heterojunction diode grown by ultrahigh vacuum chemical vapor deposition at 550-degrees-C is demonstrated. The dark current density measured at 77 K is (2.5 +/- 0.1) x 10(-7) A/cm2 for the barrier height of 176 +/- 8 meV, at a reverse bias of 1 V. The barrier heights are measured from the activation analysis of the saturation current and compared to the theoretical values. The barrier height decreases as the thickness of the SiGe strained layer exceeds the critical thickness.
EFFECTS OF DRY-ETCHING DAMAGE REMOVAL ON LOW-TEMPERATURE SILICON SELECTIVE EPITAXIAL-GROWTH
(1995-10-01)
TSENG, HC
;
CHANG, CY
;
PAN, FM
;
CHEN, LP
;
電子工程學系及電子研究所
The epitaxial silicon layer selectively grown on the reactive ion etched (RIE) silicon substrate using CF4, CHF3 and Ar etching gases has been studied. Defects and contaminants induced by the RIE process result in a rough epilayer, and degrade the current-voltage (I-V) characteristics. An interfacial carbide layer is present between the epilayer and the RIE treated substrate. Using an efficient and convenient after-etching treatment with a CF4/O-2 low-energy plasma, we obtain a clean Si surface in the patterned oxide windows for selective epitaxial growth, and the electrical characteristics are significantly improved. (C) 1995 American Institute of Physics.
EFFECTS OF DRY-ETCHING DAMAGE REMOVAL ON LOW-TEMPERATURE SILICON SELECTIVE EPITAXIAL-GROWTH
(1995-10-01)
TSENG, HC
;
CHANG, CY
;
PAN, FM
;
CHEN, LP
;
電子工程學系及電子研究所
The epitaxial silicon layer selectively grown on the reactive ion etched (RIE) silicon substrate using CF4, CHF3 and Ar etching gases has been studied. Defects and contaminants induced by the RIE process result in a rough epilayer, and degrade the current-voltage (I-V) characteristics. An interfacial carbide layer is present between the epilayer and the RIE treated substrate. Using an efficient and convenient after-etching treatment with a CF4/O-2 low-energy plasma, we obtain a clean Si surface in the patterned oxide windows for selective epitaxial growth, and the electrical characteristics are significantly improved. (C) 1995 American Institute of Physics.
EFFECTS OF POLYSILICON ELECTRON-CYCLOTRON-RESONANCE ETCHING ON ELECTRICAL CHARACTERISTICS OF GATE OXIDES
(1995-05-01)
KANG, TK
;
UENG, SY
;
DAI, BT
;
CHEN, LP
;
CHENG, HC
In spite of the small amount of damage induced by Electron Cyclotron Resonance (ECR) etching, the radiation damage due to vacuum ultraviolet (VUV) photons from the high-density plasma still causes several problems. The leakage currents of the metal-oxide-semiconductor (MOS) capacitors with ECR-etched polysilicon gates are found to be higher than those of the control with wet etching. The leakage mechanism is therefore investigated in detail. The ions and radicals of the ECR plasma can directly attack the peripheral gate oxide and form the surface-damaged layer. In addition, the VUV photons will deeply impact the oxide interior and induce positive charges and interface trap states. ii dilute HF solution can effectively remove the surface damage layer. Annealing at 400 degrees C for 30 min can eliminate completely the positive charges. Furthermore, the SiO2/Si interface trap states are completely removed as the annealing time is raised to 60 min.
EPITAXY OF SI1-XGEX BY ULTRAHIGH-VACUUM CHEMICAL-VAPOR-DEPOSITION USING SI2H6 AND GEH4
(1995-07-15)
CHEN, LP
;
CHOU, TC
;
TSAI, WC
;
HUANG, GW
;
TSENG, HC
Disilane and germane were used to grow Si1-xGex epilayers at 550 degrees C by ultrahigh-vacuum chemical vapor deposition (UHVCVD). The solid composition x and growth rate of Si1-xGex were evaluated from double-crystal X-ray rocking curves and show very strong dependence on the total source gas flow rate ([GeH4]+[Si2H6]) and the gas ratio ([GeH4]/[GeH4]+[Si2H6]). The solid composition increases with increase of the gas ratio and also with increasing the total source flux by keeping gas ratio constant. The growth rate increases with the solid composition at lower values and then becomes saturated in the higher composition range (x>0.22). The results can be explained by the relationships of the source fluxes, relative incorporation efficiency at activated surface sites and hydrogen desorption under different growth conditions.
FABRICATION OF P-CHANNEL POLYCRYSTALLINE SI1-XGEX THIN-FILM TRANSISTORS BY ULTRAHIGH-VACUUM CHEMICAL-VAPOR-DEPOSITION
(1994-09-26)
LIN, HC
;
JUNG, TG
;
LIN, HY
;
CHANG, CY
;
CHEN, LP
In this report, we present a novel approach for fabricating polycrystalline silicon-germanium thin-film transistors at low temperatures (less than or equal to 550 degrees C). A bottom gate configuration is used for this approach, and an i-Si1-xGex/i-Si/p(+)-Si1-yGey multilayer is deposited sequentially on the gate oxide using an ultra-high vacuum chemical vapor deposition technique. The i-Si1-xGex serves as the channel while the i-Si is used as a buffer layer for allowing p(+)-Si1-yGey to be etched selectively on. p-channel thin-film transistors with a held-effect mobility of 13 cm(2)/V s were achieved using this method, which is superior to those grown by low pressure chemical vapor deposition. Our results indicate that the deposition of poly-Si1-xGex/poly-Si multilayer structure would be a promising way for polycrystalline thin-film device applications.