Browsing by Author "CHEN, WS"

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A MODEL FOR BORON DEPOSITION IN SILICON USING A BBR3 SOURCE
(1982)
GUO, SF
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CHEN, WS
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交大名義發表
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電控工程研究所
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National Chiao Tung University
EFFECTS OF P+-IMPLANTED POLY-SI ELECTRODES ON THE GATE DIELECTRIC CHARACTERISTICS OF THIN OXIDES
(1991-04-01)
CHENG, HC
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CHEN, WS
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Phosphorus implantation into polycrystalline silicon (poly-Si) has been used to dope the gate electrodes in poly-Si and polycide structures. Effects of phosphorus implantation conditions and post-implantation annealing on the time zero dielectric breakdown (TZDB) characteristics of gate oxides of thickness 10, 20 and 30 nm were investigated. Higher implantation energy and higher post-implantation annealing temperature result in worse TZDB properties of the gate oxides. Especially, the TZDB characteristics of 10-nm-thick oxides after annealing show a much more significant dependence on the phosphorus implantation energy and post-implantation annealing temperature than those of thicker oxides. Therefore, phosphorus diffusion into the SiO2/Si interface is the main cause of deterioration of the gate dielectrics. The thicker oxide has a higher endurance to the phosphorus diffusion and consequently achieves a better dielectric property for the higher energy implantation and higher temperature annealing conditions.