Browsing by Author "CHEN Chih"

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CIRCUIT BOARD WITH TWINNED CU CIRCUIT LAYER AND METHOD FOR MANUFACTURING THE SAME
(2014-04-17)
CHEN Chih
;
LIN Han-Wen
A circuit board with twinned Cu circuit layer and a method for manufacturing the same are disclosed, wherein the method comprises the following steps: (A) providing a substrate with a first circuit layer formed thereon, wherein the first circuit layer comprises a conductive pad; (B) forming a first dielectric layer on the surface of the substrate; (C) forming plural openings in the first dielectric layer, wherein each opening penetrates through the first dielectric layer and communicates with the conductive pad to expose the conductive pad; (D) forming a Cu seeding layer in the openings; (E) forming a nano-twinned Cu layer in the openings with an electroplating process; and (F) annealing the substrate to transfer the material of the Cu seeding layer into nano-twinned Cu, wherein the nano-twinned Cu layer and the transferred Cu seeding layer are formed into a second circuit layer.
Electric connecting structure comprising preferred oriented Cu6Sn5 grains and method for fabricating the same
(2013-11-14)
CHEN Chih
;
LIN Han-Wen
An electric connecting structure comprising preferred oriented Cu6Sn5 grains and a method for fabricating the same are disclosed. The method of the present invention comprises steps: (A) providing a first substrate; (B) forming a first nano-twinned copper layer on part of a surface of the first substrate; (C) using a solder to connect the first substrate with a second substrate having a second electrical pad, in which the second electrical pad comprises a second nano-twinned copper layer, and the solder locates between the first nano-twinned copper layer and the second nano-twinned copper layer; and (D) reflowing at the temperature of 200° C. to 300° C. to transform at least part of the solder into an intermetallic compound (IMC) layer, in which the IMC layer comprises plural Cu6Sn5 grains with a preferred orientation; wherein at least 50% in volume of the first and second nano-twinned copper layer comprises plural grains.
Electrical Connecting Element and Method for Manufacturing the Same
(2014-08-07)
CHEN Chih
;
LIU Taochi
;
HUANG Yi-Sa
;
LIU Chien-Min
An electrical connecting element for connecting a first substrate and a second substrate and a method for manufacturing the same are disclosed. The method of the present invention comprises: (A) providing a first substrate and a second substrate, wherein a first copper film is formed on the first substrate, a first metal film is formed on the second substrate, a first connecting surface of the first copper film has a (111)-containing surface, and the first metal film has a second connecting surface; and (B) connecting the first copper film and the first metal film to form an interconnect, wherein the first connecting surface of the first copper film is faced to the second connecting surface of the first metal film.
ELECTRICAL CONNECTING ELEMENT HAVING NANO-TWINNED COPPER, METHOD OF FABRICATING THE SAME, AND ELECTRICAL CONNECTING STRUCTURE COMPRISING THE SAME
(2014-04-03)
CHEN Chih
;
CHIU Wei-Lan
An electrical connecting element, a method of fabricating the same, and an electrical connecting structure comprising the same are disclosed. The method of fabricating the electrical connecting structure having twinned copper of the present invention comprises steps of: (A) providing a first substrate; (B) forming a nano-twinned copper layer on part of a surface of the first substrate; (C) forming a solder on the nano-twinned copper layer of the first substrate; and (D) reflowing the nano-twinned Cu layer and solder to produce a solder joint, wherein at least part of the solder reacts with the nano-twinned copper layer to produce an intermetallic compound (IMC) layer which comprises a Cu3Sn layer, This invention reduces the voids formation in the interface between the intermetallic compound and the solder, and then enhances the reliability of solder joints.
Electrodeposited Nano-Twins Copper Layer and Method of Fabricating the Same
(2013-05-16)
CHEN Chih
;
TU King-Ning
;
LIU Taochi
An electrodeposited nano-twins copper layer, a method of fabricating the same, and a substrate comprising the same are disclosed. According to the present invention, at least 50% in volume of the electrodeposited nano-twins copper layer comprises plural grains adjacent to each other, wherein the said grains are made of stacked twins, the angle of the stacking directions of the nano-twins between one grain and the neighboring grain is between 0 to 20 degrees. The electrodeposited nano-twins copper layer of the present invention is highly reliable with excellent electro-migration resistance, hardness, and Young's modulus. Its manufacturing method is also fully compatible to semiconductor process.
METHOD FOR INHIBITING GROWTH OF INTERMETALLIC COMPOUNDS
(2013-02-14)
CHEN Chih
;
TU King-Ning
;
HSIAO Hsiang-Yao
The present invention relates to a method for inhibiting growth of intermetallic compounds, comprising the steps of: (i) preparing a substrate element including a substrate on which at least one layer of metal pad is deposited, wherein at least one thin layer of solder is deposited onto the layer of metal pad, and then carry out reflowing process; and (ii) further depositing a bump of solder with an appropriate thickness on the substrate element, characterized in that a thin intermetallic compound is formed by the reaction of the thin solder layer and the metal in the metal pad after appropriate heat treatment of the thin solder layer. In the present invention, the formation of a thin intermetallic compound is able to slow the growth of the intermetallic compound and to prevent the transformation of the intermetallic compounds.
SINGLE CRYSTAL COPPER, MANUFACTURING METHOD THEREOF AND SUBSTRATE COMPRISING THE SAME
(2015-03-05)
CHEN Chih
;
TU King-Ning
;
LU Chia-Ling
The present invention relates to a single crystal copper having [100] orientation and a volume of 0.1˜4.0×106 μm3. The present invention further provides a manufacturing method for the single crystal copper and a substrate comprising the same.
SPECIMEN BOX FOR ELECTRON MICROSCOPE
(2013-01-10)
CHEN Chih
;
TU King-Ning
The present invention relates to a specimen box for an electron microscope, which comprises a first substrate, a second substrate, and a metal adhesion layer. The first substrate has a first surface, a second surface, a first concave, and one or more first through holes, wherein the first through hole penetrates through the first substrate. The second substrate has a third surface, a forth surface, and a second concave. Besides, the metal adhesion layer is disposed between the first substrate and the second substrate to form a space for a specimen placed therein. In addition, the specimen box of the present invention further comprises one or more plugs. When the plug is assembled into the first through hole to seal the specimen box, the in-situ observation can be accomplished by using an electron microscope.
SPECIMEN BOX FOR ELECTRON MICROSCOPE
(2013-01-10)
CHEN Chih
;
Tu King-Ning
The present invention relates to a specimen box for an electron microscope, comprising a first substrate, a second substrate, one or more photoelectric elements, and a metal adhesion layer. The first substrate has a first surface, a second surface, a first concave, and one or more first through holes, wherein the first through holes penetrate through the first substrate. The second substrate has a third surface, a forth surface, and a second concave. The photoelectric element is disposed between the first substrate and the second substrate. In addition, the metal adhesion layer is disposed between the first substrate and the second substrate to form a space for a specimen contained therein. Besides, the present specimen box further comprises one or more plugs. When the plugs are assembled into the first through holes to seal the specimen box, the in-situ observation can be accomplished by using the electron microscope.
STRUCTURE FOR MEASURING BUMP RESISTANCE AND PACKAGE SUBSTRATE COMPRISING THE SAME
(2012-10-25)
CHEN Chih
;
Chang Yuan-Wei
A structure for measuring bump resistance and a package substrate comprising the same are disclosed, the structure for measuring bump resistance of the present invention comprises: plural connecting bumps arranged in a row; at least one first connecting element; and at least one second connecting element; wherein the nth connecting bump and the (n+1)th connecting bump connect by the first connecting element, the (n+1)th connecting bump and the (n+2)th connecting bump connect by the second connecting element, n is an odd number of 1 or more; the first connecting element connects with a first voltage-measurement pad; the second connecting element connects with an auxiliary pad, the auxiliary pad connects with an auxiliary bump, a second voltage-measurement pad connects with the auxiliary bump.