Browsing by Author "CHENG, HC"

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A NEW ANALYTICAL EXPRESSION FOR THE INTERFACE INDEX OF METAL SCHOTTKY CONTACTS ON SEMICONDUCTORS
(1995-05-01)
SZE, JJ
;
CHENG, HC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
By reconsidering the effect of the penetration depth of the interface states, a new analytical expression of the interface index has been achieved to successfully explain the role of the semiconductor ionicity in the behavior of metal-Schottky contacts on semiconductors. The derived interface indices not only fit quite well with the previous experimental data but also exhibit a sharp transition from the Bardeen limit to the Schottky limit for semiconductor ionicity around 0.8, which agrees well with the experiment reports.
A NEW FABRICATION TECHNOLOGY FOR FIELD-EMISSION TRIODES WITH EMITTER-GATE SEPARATION OF 0.18-MU-M
(1995-01-01)
WANG, CC
;
LEE, WF
;
KU, TK
;
CHEN, MS
;
FENG, MS
A new fabrication technology has been used for field-emission triodes with the emitter-gate separation as small as 0.18 mum to reduce the turn-on and anode voltages. The technology is based on the thermal oxidation of silicon and low-pressure chemical vapor deposition (LPCVD) of polycrystalline silicon, making the fabrication of a sub-half-micronmeter gate opening easy and reproducible. The entire process requires use of only one photolithography mask, and does not require advanced high-resolution photolithographic techniques. In this device, the oxidation process serves the three purposes of sharpening the emitters, defining the emitter-gate separation, and achieving a high-quality insulator. The finished devices have the emitter situated exactly at the center of the gate opening due to a self-alignment process. Furthermore, the LPCVD polysilicon film can form gate electrodes with a smooth edge and a small gate opening due to excellent step coverage.
A NEW OXIDATION-RESISTANT COSI2 PROCESS FOR SELF-ALIGNED SILICIDATION (SALICIDE) TECHNOLOGY
(1993-01-01)
LOU, YS
;
WU, CY
;
CHENG, HC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a new oxidation-resistant and self-aligned CoSi2 process using amorphous-Si (a-Si)/Co bilayer metallization. It is shown that, even in an environment without introducing any flowing inert gas, the detrimental reaction between Co metal and ambient impurities, e.g. O2 and H2O, can be completely impeded by a covered thin a-Si layer during the thermal silicidation cycle. Moreover, despite a capped a-Si layer over Co film, the satisfactory self-aligned silicidation properties can be retained if the initial silicidation temperature is kept below 500-degrees-C in N2 ambient. Furthermore, the dependences of both oxidation-resistant and self-aligned silicidation properties on the thicknesses of a-Si and Co films are studied in detail. Based on experimental analysis, the allowed process window for the a-Si film thickness can be determined and is shown to increase with increasing the Co film thickness. An empirical process rule is experimentally obtained to determine the optimal thickness relation between a-Si and Co films for the a-Si/Co bilayer process. Thus, a simple and practical self-aligned CoSi2 process with extremely high immunity to ambient impurities is proposed for SALICIDE applications.
A NEW PORTRAYAL OF OXIDATION OF UNDOPED POLYCRYSTALLINE SILICON FILMS IN A SHORT-DURATION
(1994-01-01)
WANG, PW
;
SU, HP
;
TSAI, MJ
;
HONG, G
;
FENG, MS
Both polysilicon films low-pressure chemical-vapor-deposited (LPCVD) at 625 degrees C and amorphous films deposited at 550 degrees C with subsequent annealing at 600 degrees C for 24 h to form polysilicon films were used to grow polyoxides at 850 degrees C in wet or dry oxygen. Detailed high-resolution transmission electron microscopy (HRTEM) and X-ray diffraction (XRD) studies have been performed to determine the microstructures of the polyoxide/polysilicon interface and the crystallinity of the polysilicon films. It is found that the oxidation phenomena of these two films are very different. For the recrystallized amorphous silicon specimens, the polyoxide/polysilicon interface is very flat because of the poor crystallinity and low-angle grain boundaries between the grains. On the other hand, the polyoxide/polysilicon interface is rough for the as-deposited polysilicon samples due to the distinct grain characteristics and the high-angle grain boundaries between these grains.
A SILICIDATION-INDUCED PROCESS CONSIDERATION FOR FORMING SCALE-DOWN SILICIDED JUNCTION
(1994-09-01)
CHENG, HC
;
JUANG, MH
;
LIN, CT
;
HUANG, LM
;
電子工程學系及電子研究所
A process consideration for forming silicided shallow junctions, arising from silicidation process, has been discussed. The CoSi2 shallow p+n junctions formed by various schemes are characterized. The scheme that implants BF2+ ions into thin Co films on Si substrates and subsequent silicidation yields good junctions, but the problems about the dopant drive-in and knock-on of metal deeply degrade this scheme. In the regime that implants the dopant into Si and then Co deposition, however, a large perimeter leakage of 0.1 nA/cm is caused. Generation current, associated with a defect-enhanced diffusion of Co in Si during silicidation, dominates the leakage. A high-temperature pre-activation prior to Co deposition reduces the perimeter leakage to 0.038 nA/cm, but which deepens the junctions.
ACTIVATION MECHANISM OF IMPLANTED BORON IN A SI SUBSTRATE
(1992-12-01)
JUANG, MH
;
CHENG, HC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The recrystallization and dopant activation in the BF2+ implanted samples with a 110 keV/5 X 10(15) cm-2 condition into a Si substrate and annealed with different heating rates to various preset temperatures for zero holding time have been studied. A higher heating rate yielded a higher carrier mobility and a better crystallinity. A statistical model was proposed to characterize the dopant activation. The activated dopant concentration n was expressed as gamma exp(-E(a)/kT). The pre-exponential term gamma is a function of critical temperature T(c) due to a finite melting point of Si, and heating rate. Both the effective activation energy E(a) and T(c) values decreased with increasing heating rate. With increasing heating rate, the gamma term rapidly decreased at low rates due to the shortened effective annealing time, but showed slight increase at high rates due to the decreased T(c) value. Low heating rates facilitated the dopant activation via the gamma term, while high heating rates enhanced the activation efficiency via the E(a) term.
ANOMALOUS BIAS-STRESS-INDUCED UNSTABLE PHENOMENA OF HYDROGENATED AMORPHOUS-SILICON THIN-FILM TRANSISTORS
(1995-10-23)
TAI, YH
;
TSAI, JW
;
CHENG, HC
;
SU, FC
;
電子工程學系及電子研究所
Thin-film transistors (TFTs) with different silicon nitride (SiNx) gate compositions and various hydrogen concentrations in their amorphous silicon films (a-Si:H) have been stressed with positive and negative biases to realize the instability mechanisms. For both stress polarities, it is found that the threshold voltage shifts significantly increase due to the trap sites in the SiNx gate. As the effects of the trapped charges in the SiNx films are reduced, the anomalous threshold voltage shifts under negative stress voltage are observed. The creation of the states near the conduction band in the a-Si:H films can be enhanced according to the defect pool concept and stimulated by the hydrogen contents in the a-Si:H films, which can be confirmed by the subthreshold swing change. Therefore, the negative threshold voltage shifts caused by the hole trapping in the SiN, gate are positively compensated by the created states, reflecting the turnaround behaviors for the threshold voltage shifts. As for the positive stress, the state creation in the a-Si:H films can be suppressed via the defect pool mechanism and thus the threshold voltage shifts are dominantly affected by the electron trapping in the SiNx gates. (C) 1995 American Institute of Physics.
ANOMALOUS BIAS-STRESS-INDUCED UNSTABLE PHENOMENA OF HYDROGENATED AMORPHOUS-SILICON THIN-FILM TRANSISTORS
(1995-10-23)
TAI, YH
;
TSAI, JW
;
CHENG, HC
;
SU, FC
;
奈米中心
Thin-film transistors (TFTs) with different silicon nitride (SiNx) gate compositions and various hydrogen concentrations in their amorphous silicon films (a-Si:H) have been stressed with positive and negative biases to realize the instability mechanisms. For both stress polarities, it is found that the threshold voltage shifts significantly increase due to the trap sites in the SiNx gate. As the effects of the trapped charges in the SiNx films are reduced, the anomalous threshold voltage shifts under negative stress voltage are observed. The creation of the states near the conduction band in the a-Si:H films can be enhanced according to the defect pool concept and stimulated by the hydrogen contents in the a-Si:H films, which can be confirmed by the subthreshold swing change. Therefore, the negative threshold voltage shifts caused by the hole trapping in the SiN, gate are positively compensated by the created states, reflecting the turnaround behaviors for the threshold voltage shifts. As for the positive stress, the state creation in the a-Si:H films can be suppressed via the defect pool mechanism and thus the threshold voltage shifts are dominantly affected by the electron trapping in the SiNx gates. (C) 1995 American Institute of Physics.
CHARACTERISTICS OF POLYCRYSTALLINE SILICON THIN-FILM TRANSISTORS WITH THIN OXIDE NITRIDE GATE STRUCTURES
(1993-08-01)
CHENG, HC
;
TAI, YH
;
FENG, MS
;
WANG, JJ
;
材料科學與工程學系
Polycrystalline silicon (poly-Si) thin-film transistors (TFTs) with thin oxide/nitride (O/N) structures as gate dielectrics are fabricated. Various gate dielectrics, i.e., high-temperature thermal oxides with different thicknesses, low-pressure chemical-vapor-deposited silicon nitrides, and different combinations of O/N structures with various thicknesses, are performed to study their effects on poly-Si TFTs. The effective carrier mobility of devices with thin gate oxides is several times larger than of those with thick gate oxides. However, the breakdown voltages of thin gate oxides are too low to satisfy the requirements of TFT applications. Silicon nitrides can be substituted because of the high breakdown voltage and the smooth dielectric/poly-Si interfaces. A problem in adopting silicon nitride is the large interface stress between the silicon nitride and the poly-Si. A thin thermal pad oxide beneath the silicon nitride is therefore grown to reduce the high interface stress. Finally, the equivalent oxide thickness effect of the O/N gate structures on the electrical characteristics of TFTs is systematically investigated.
CHARACTERIZATION OF A HIGH-QUALITY AND UV-TRANSPARENT PECVD SILICON-NITRIDE FILM FOR NONVOLATILE MEMORY APPLICATIONS
(1994)
WANG, CK
;
YING, TL
;
WEI, CS
;
LIU, LM
;
CHENG, HC
CHARACTERIZATION OF H-2/N-2 PLASMA PASSIVATION PROCESS FOR POLY-SI THIN-FILM TRANSISTORS (TFTS)
(1995-06-01)
TSAI, MJ
;
WANG, FS
;
CHENG, KL
;
WANG, SY
;
FENG, MS
The effects of nitrogen additives on the plasma hydrogenation of polycrystalline silicon thin film transistors (poly-Si TFTs) have been investigated with various radio-frequency (RF) power densities, substrate heating temperature, gas flow rates, as well as chamber pressures. The nitrogen-containing hydrogen (H-2/N-2) plasma treatments show better passivation effects on the electrical characteristics of the poly-Si TFTs than the pure H-2 hydrogenation. It is attributed to the passivation effect of the nitrogen radicals themselves and the promotion of the hydrogen plasma generation due to the radical collision. The passivation effects have been enhanced by properly chosen RF power density, gas flow rate and chamber pressure. Furthermore, the H-2/N-2 plasma were also utilized to passivate the poly-Si TFTs with different grain structures.
CHARACTERIZATION OF SILICIDED SHALLOW N+P JUNCTIONS FORMED BY P+ IMPLANTATION INTO THIN TI FILMS ON SI SUBSTRATES
(1992-10-01)
JUANG, MH
;
CHENG, HC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
High-quality silicided shallow n+p junctions have been fabricated by P+ implantation into thin Ti films on Si substrates and by moderate implant conditions as well as subsequent high-temperature rapid thermal annealing (RTA) followed by low-temperature conventional furnace annealing (CFA). RTA minimizes the diffusion of knock-on Ti but greatly reduces the drive-in efficiency because of its short annealing time. Driving the dopants out of silicides via long-time annealing was associated with the crystallinity of silicides. The junctions formed by this scheme with respect to various implant and anneal conditions have been characterized. In addition, the distribution profile of Ti penetration was correlated with the effective generation life time obtained from the reverse I-V curves.
CONVENTIONAL FURNACE AND RAPID THERMAL ANNEALING OF COBALT FILMS ON SI(111)
(1992-09-15)
JUANG, MH
;
CHENG, HC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The effects of conventional furnace annealing (CFA) and rapid thermal annealing (RTA) on the interfacial reactions of thin cobalt films on Si(111) have been investigated. The low heating rates (about 10-degrees-C s-1) associated with CFA lead to impurity segregation at the silicide-Si interface during the initial stage of interfacial reactions, while segregation is absent for high heating rates (about 100-degrees-C s-1) associated with RTA. From examination by transmission electron microscopy (TEM), RTA promotes uniform formation of silicides and epitaxial growth of twin-structure CoSi2, causing an average grain size of about 50 nm and a surface coverage area of about 70% at 500-600-degrees-C for 100-600 s. In contrast. silicidation is retarded for CFA, and grain growth is preferred to formation of epitaxial CoSi2. The electrical characterization of low doping level silicided shallow junctions correlates well with the TEM examinations of the interfacial reactions by the respective annealing schemes.
CROSS-SECTIONAL TRANSMISSION ELECTRON-MICROSCOPE STUDY OF THE GROWTH-KINETICS OF HEXAGONAL MOSI2 ON (001)SI
(1987-03-15)
CHENG, JY
;
CHENG, HC
;
CHEN, LJ
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
EFFECT OF SIH4/CH4 FLOW RATIO ON THE GROWTH OF BETA-SIC ON SI BY ELECTRON-CYCLOTRON-RESONANCE CHEMICAL-VAPOR-DEPOSITION AT 500-DEGREES-C
(1995-01-09)
LIU, CC
;
LEE, CY
;
CHENG, KL
;
CHENG, HC
;
YEW, TR
EFFECTS OF COBALT SILICIDATION ON THE ELECTRICAL CHARACTERISTICS OF SHALLOW P(+)N JUNCTIONS FORMED BY BF2+ IMPLANTATION INTO THIN POLYCRYSTALLINE SI FILMS
(1995-03-01)
LIN, CT
;
CHAO, CH
;
JUANG, MH
;
JAN, ST
;
CHOU, PF
Excellent shallow p(+)n junctions have been formed by implanting BF2+ ions into thin polycrystalline Si films and subsequent annealing. The samples implanted at 50 keV to a dose 5 x 10(15) cm(-2) show a leakage of 1 nA/cm(2) and a junction depth of about 0.05 mu m after a 800 degrees C annealing. To reduce the series resistances of the junctions, silicidation with different col;alt thickness was used to drive the as-implanted dopants in the polysilicon films into the resultant junctions of the silicon substrates. For the low energy implantation at 50 keV at all dosages, silicidation can result in poor electrical characteristics due to the confinement of the dopants by the silicidation process. On the other hand, the electrical characteristics can be retained when a higher implantation energy of 100 keV with a dosage higher than 5 x 10(15) cm 2 was used. In addition, the samples implanted at 125 keV show poor electrical characteristics for the nonsilicided junctions but good characteristics after the silicidation. It is attributed to the enhanced defect annihilation by the formed silicide. Furthermore, silicided implanted through poly-Si junctions with excellent characteristics can be fabricated after a low temperature (600 degrees C) annealing if the samples are implanted at 100 keV with a dosage higher than 5 X 10(15) cm(-2).
EFFECTS OF P+-IMPLANTED POLY-SI ELECTRODES ON THE GATE DIELECTRIC CHARACTERISTICS OF THIN OXIDES
(1991-04-01)
CHENG, HC
;
CHEN, WS
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Phosphorus implantation into polycrystalline silicon (poly-Si) has been used to dope the gate electrodes in poly-Si and polycide structures. Effects of phosphorus implantation conditions and post-implantation annealing on the time zero dielectric breakdown (TZDB) characteristics of gate oxides of thickness 10, 20 and 30 nm were investigated. Higher implantation energy and higher post-implantation annealing temperature result in worse TZDB properties of the gate oxides. Especially, the TZDB characteristics of 10-nm-thick oxides after annealing show a much more significant dependence on the phosphorus implantation energy and post-implantation annealing temperature than those of thicker oxides. Therefore, phosphorus diffusion into the SiO2/Si interface is the main cause of deterioration of the gate dielectrics. The thicker oxide has a higher endurance to the phosphorus diffusion and consequently achieves a better dielectric property for the higher energy implantation and higher temperature annealing conditions.
EFFECTS OF POLYSILICON ELECTRON-CYCLOTRON-RESONANCE ETCHING ON ELECTRICAL CHARACTERISTICS OF GATE OXIDES
(1995-05-01)
KANG, TK
;
UENG, SY
;
DAI, BT
;
CHEN, LP
;
CHENG, HC
In spite of the small amount of damage induced by Electron Cyclotron Resonance (ECR) etching, the radiation damage due to vacuum ultraviolet (VUV) photons from the high-density plasma still causes several problems. The leakage currents of the metal-oxide-semiconductor (MOS) capacitors with ECR-etched polysilicon gates are found to be higher than those of the control with wet etching. The leakage mechanism is therefore investigated in detail. The ions and radicals of the ECR plasma can directly attack the peripheral gate oxide and form the surface-damaged layer. In addition, the VUV photons will deeply impact the oxide interior and induce positive charges and interface trap states. ii dilute HF solution can effectively remove the surface damage layer. Annealing at 400 degrees C for 30 min can eliminate completely the positive charges. Furthermore, the SiO2/Si interface trap states are completely removed as the annealing time is raised to 60 min.
EFFECTS OF POSTETCHING TREATMENTS ON ELECTRICAL CHARACTERISTICS OF THERMAL OXIDES ON REACTIVE-ION-ETCHED SILICON SUBSTRATES
(1995-09-01)
CHENG, HC
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UENG, SY
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WANG, PW
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KANG, TK
;
CHAO, TS
Thin oxides thermally grown on the reactive-ion-etched (RIE) silicon substrates in N2O and diluted O-2 ambients have been studied. The RIE will strongly affect the silicon surface microroughness and lead to poor oxides properties. Using the after-treatment-chamber (ATC) process, CF4 addition in the O-2 plasma can further improve the time-zero-to-dielectric-breakdown (TZDB) characteristics of the thin oxides as compared with pure O-2 plasma. This is because CF4 addition in the ATC can remove the damaged silicon layer and smooth the silicon surface since the (O)2 plasma can effectively only strip the polymeric layer. In addition, the N2O-grown oxides can enlarge the process window of the CF4/O-2 ATC treatments with respect to pure oxides.
EFFECTS OF RAPID THERMAL ANNEALING ON THE FORMATION OF SHALLOW P+N JUNCTION BY IMPLANTING BF2+ IONS INTO THIN METAL-FILMS ON SI SUBSTRATE .1. THIN TITANIUM FILMS
(1992-02-01)
JUANG, MH
;
CHENG, HC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
High-quality Ti-silicided shallow p+ n junctions have been fabricated by implanting BF2+ ions into thin Ti films on Si substrate and subsequent silicidation/drive-in by rapid thermal annealing (RTA) or conventional furnace annealing (CFA) under proper implant and anneal conditions. For both the RTA and CFA techniques, annealing temperatures higher than 800-degrees-C degrade the junction formation because of more severe dopant confinement within the silicides and more serious diffusion of knock-on Ti into junction regions. The high-dose implant greatly enhanced the dopant activation and thus improved the junctions. The high heating rate for RTA caused an immediate formation of Ti-B compounds at high temperatures, while CFA considerably promoted the drive-in efficiency because of its low heating rates and long annealing times. Hence, CFA yielded better low-bias rectifying characteristics than RTA due to larger dopant activation. However, CFA caused much worse high reverse-bias characteristics. A rapid increase of reverse currents with bias voltage was observed for the CFA-treated samples, indicating a severe Ti penetration due to long annealing times.