Browsing by Author "CHENG, KH"

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A new CMOS current-sensing complementary pass-transistor logic (CSCPTL) for high-speed low-voltage applications
(1995)
WU, CY
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CHENG, KH
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LU, JH
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
ANALYSIS AND DESIGN OF A NEW RACE-FREE 4-PHASE CMOS LOGIC
(1993-01-01)
WU, CY
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CHENG, KH
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WANG, JS
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, a new four-phase dynamic logic, called the high-speed precharge-discharge CMOS logic (HS-PDCMOS logic), is proposed and analyzed. Basically the HS-PDCMOS logic uses two different units to implement the logic function and to drive the output load separately. Thus, a complex function can be implemented within a single gate and form the pipelined structured as well. The HS-PDCMOS logic needs four operation clocks and has three different versions. An experimental chip has been designed and measured to partly verify the results of circuit analysis and simulation. It is shown that the HS-PDCMOS logic has an operation speed about 2.5 to 3 times higher than the conventional four-phase dynamic logic. Moreover, the new logic has no clock skew, race, and charge redistribution problems. These advantages make the HS-PDCMOS logic very promising in high-speed complex VLSI design.
FEEDBACK-CONTROLLED ENHANCE-PULL-DOWN BICMOS FOR SUB-3-V DIGITAL CIRCUIT
(1994)
TSENG, YK
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CHENG, KH
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WU, CY
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
LATCHED CMOS DIFFERENTIAL LOGIC (LCDL) FOR COMPLEX HIGH-SPEED VLSI
(1991-09-01)
WU, CY
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CHENG, KH
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new CMOS differential logic, called the latched CMOS differential logic (LCDL), is proposed and analyzed. LCDL circuits can implement a complex combinational logic function in a single gate, and form the pipeline structure as well. It is shown that the LCDL with a fan-in number between 6 and 15 has the highest operation speed among those differential logic circuits. It is also free from charge-sharing, clock-skew, and race problems. Experimental results have verified the high speed and race-free performance of the proposed LCDL.