Browsing by Author "CHENG, MH"

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DESIGN OF SINUSOIDAL OSCILLATORS USING THE THEORY OF VARIABLE STRUCTURE SYSTEMS
(1992-01-01)
CHEN, YP
;
CHENG, MH
;
交大名義發表
;
電控工程研究所
;
National Chiao Tung University
This paper presents a new simple scheme to design sinusoidal oscillators by using the theory of variable structure systems. The desired oscillation frequency and amplitude can be independently determined. Significantly, the total system of the sinusoidal oscillator is easily completed by choosing two linear second-order subsystems with some appropriate switching conditions and the required circuit components for the developed system are all commercially available.
MODEL-REDUCTION FOR CONTINUOUS-TIME AND DISCRETE-TIME-SYSTEMS VIA SQUARED-MAGNITUDE RESPONSES MATCHING BY LINEAR-PROGRAMMING
(1991-04-01)
CHENG, MH
;
CHANG, JY
;
交大名義發表
;
電控工程研究所
;
National Chiao Tung University
The use of linear programming technique for the model reduction of continuous- and discrete-time systems is discussed. Based on squared-magnitude responses between the original system and its reduced model, a novel error function is presented. Two linear programming formulations are presented that use the L1-norm and the L infinity-norm of the proposed error function as respective criteria to solve the squared-magnitude problem. Finally, the reduced model is obtained by applying the factorization technique. Since the poles of the obtained squared-magnitude function are prevented from occurring on the j-omega axis (continous-time case) or unit circle (discrete-time case) by constraint, this approach ensures the stability of the reduced model. Some examples illustrate its applicability.
SWITCHED-CAPACITOR PIPELINED LOGARITHMIC A/D AND D/A CONVERTERS
(1991-12-01)
CHENG, MH
;
HUANG, TC
;
交大名義發表
;
電控工程研究所
;
National Chiao Tung University
The paper presents two switched-capacitor circuits with modest complexity to implement a pipelined logarithmic digital-analogue convertor (LDAC) and logarithmic analogue-digital convertor (LADC), respectively, which spend only one clock time per conversion. In addition, the effect of the capacitor-ratio mismatch on the conversion errors of the convertor circuits is discussed. Hence, from the available maximum capacitor-ratio value and mismatch of the present integrated circuit (IC) technology, the feasible bit length of the pipelined LDAC and LADC can be computed.