Browsing by Author "CHIN, SP"

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A NEW 2-DIMENSIONAL MODEL FOR THE POTENTIAL DISTRIBUTION OF SHORT GATE-LENGTH MESFETS AND ITS APPLICATIONS
(1992-08-01)
CHIN, SP
;
WU, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new analytical technique for calculating the two-dimensional (2D) potential distribution of a MESFET device operated in the subthreshold region is proposed, in which the 2D Poisson's equation is solved by the Green's function technique. The potential and electric-field distributions of a non-self-aligned MESFET device are calculated exactly from different types of Green's function in different boundary regions, and the sidewall potential at the interface between these regions can be determined by the continuation of the electric field at the sidewall boundary. The remarkable feature of the proposed method is that the implanted doping profile in the active channel can be treated. Furthermore, a simplified technique is developed to derive a set of quasi-analytical models for the side-wall potential at both sides of the gate edge, the threshold voltage of short gate-length devices, and the drain-induced barrier lowering. Moreover, the developed quasi-analytical models are compared with the results of 2D numerical analysis and good agreements are obtained.
A NEW GRID-GENERATION METHOD FOR 2-D SIMULATION OF DEVICES WITH NONPLANAR SEMICONDUCTOR SURFACE
(1993-09-01)
CHIN, SP
;
WU, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A general analytical method is proposed to transform a 2-D multilayer physical domain with the nonplanar semiconductor surface into a 2-D rectangular mathematical domain with the planar surface, in which a set of Fourier series are used to describe a general conformal mapping for each layer. Based on the proposed method, a simple iteration algorithm, which incorporates a nonlinear Jacobian-iteration method with the fast- Fourier transformation (FFT), is developed to solve a system of nonlinear equations due to the mutually coupled boundary conditions. As a result of the analytical conformal mapping, a regular, deformable grid-structure can be applied to simulate the device structure with the nonplanar semiconductor surface, and the device simulator using the conventional rectangle-based grid can be easily modified to simulate the device with the nonplanar semiconductor surface.
A NEW IV MODEL FOR SHORT GATE-LENGTH MESFETS
(1993-04-01)
CHIN, SP
;
WU, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new I-V model for short gate-length MESFET's operated in the turn-on region is proposed, in which the two-dimensional potential distribution contributed by the depletion-layer charges under the gate and in the ungate region are separately obtained by conventional 1D approximation and Green's function solution technique. Moreover, the bias-dependent parasitic resistances due to the modulation of depletion layer in the ungate region for non-self-alignment MESFET's are also taken into account in the developed I-V model. It is shown that good agreements are obtained between the developed new I-V model and the results of 2D numerical analysis. Moreover, comparisons between the proposed analytical model and the experimental data are made and excellent agreements are obtained.
A NEW METHODOLOGY FOR 2-DIMENSIONAL NUMERICAL-SIMULATION OF SEMICONDUCTOR-DEVICES
(1992-12-01)
CHIN, SP
;
WU, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new methodology for obtaining the self-consistent solution of semiconductor device equations discretized in the finite-difference scheme is proposed, in which a new discretized Green's function solution method is used to solve the two-dimensional discretized Poisson's equation and a surface mapping technique is developed to treat arbitrary surface boundary conditions. As a result of the proposed new solution method, the two-dimensional potential distribution can be expressed in terms of charge density distribution and bias conditions. Using the derived potential distribution, the SLOR-nonlinear iteration for the current continuity equations of both carriers can be performed by incorporating with a new algorithm to get the self-consistent solution of full set of semiconductor device equations without any outer iteration. Comparisons between the proposed method and the Gummel's method in Si-MESFET simulation are made. It is demonstrated that the convergent rate of the proposed method can be speeded up to 4-8 times over the Gummel's method. The proposed new iterative method can be incorporated with the conventional solution method such as the Gummel's method to get a stable and efficient computation scheme for device simulation.