Browsing by Author "CHOU, JW"

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A NEW DRAIN ENGINEERING STRUCTURE-SCD-LDD (SURFACE COUNTER DOPED LDD) FOR IMPROVED HOT-CARRIER RELIABILITY
(1993-09-01)
CHOU, JW
;
CHANG, CY
;
HO, LT
;
KO, J
;
HSUE, P
A new SCD-LDD (Surface Counter Doped LDD) structure is proposed. This structure introduces an additional oblique BF2 implant after nLDD implant, which counter-dopes the nLDD surface concentration near the gate edge. As a result, the lateral electric fields beneath the gate were reduced and the saturation drain current was conducted downward away from the maximum electric fields, resulting in a substantial enhancement of hot carrier reliability due to suppression of hot carrier generation and injection with this structure.
ANOMALOUS REVERSE SHORT-CHANNEL EFFECT IN P+ POLYSILICON GATED P-CHANNEL MOSFET
(1994-11-01)
CHANG, CY
;
LIN, CY
;
CHOU, JW
;
HSU, CCH
;
PAN, HT
The boron-penetration-dependent Reverse Short Channel Effect (RSCE) on the threshold voltage is observed for short channel p+ poly-gate PMOSFET's. The RSCE is found to be more significant as the boron penetration becomes more severe. The RSCE is significant in BF2 doped poly-gated MOS devices and is alleviated in buffered poly-gated MOS devices. Fluorine enhanced boron diffusion in the gate oxide during high temperature process is believed to account for the RSCE, which is also confirmed by using a two-dimensional process simulator.
INTERFACE-TRAP EFFECT ON GATE INDUCED DRAIN LEAKAGE CURRENT IN SUBMICRON N-MOSFETS
(1994-12-01)
WANG, TH
;
HUANG, CM
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CHANG, TE
;
CHOU, JW
;
CHANG, CY
An interface trap assisted tunneling mechanism which includes hole tunneling from interface traps to the valence band and electron tunneling from interface traps to the conduction band is presented to model the drain leakage current in a 0.5 mu m LATID N-MOSFET. In experiment, the interface traps were generated by hot carrier stress, The increased drain leakage current due to the band-trap-band tunneling can be adequately described by an analytical expression of Delta I-d = A exp(-Bit/F) with a value of B-it of 13 MV/cm, which is much lower than that (36 MV/cm) of direct band-to-band tunneling.
NEW LARGE-ANGLE TILT IMPLANTED DRAIN STRUCTURE - SURFACE COUNTER-DOPED-LIGHTLY DOPED DRAIN FOR HIGH HOT-CARRIER RELIABILITY
(1994-07-01)
CHOU, JW
;
CHANG, CY
;
HUANG, C
;
HO, LT
;
KO, J
A new surface counterdoped-lightly doped drain (SCD-LDD) structure with large angle tilt (LAT) implantation is proposed in this study. This structure introduces an additional larger tilt angle and lower-energy BF2 implant after the n- implant, which counterdopes the n- surface concentration to achieve a gate/n- fully overlapped, buried and sloped n- region inside the gate edge. As a result, the lateral electric fields inside the gate edge are reduced and pushed deeper into the substrate. In addition to a reduction in substrate current, this profile also suppresses hot carrier injection by driving the current away from the surface and the maximum electric field; then it shifts the avalanche region further into the bulk Si. This consequently produces a more effective enhancement of hot carrier reliability than that of conventional LDD's and controlled large-angle-tilt implanted drains (LATID's) for submicron VLSI circuits under 5 V operation. In conclusion, this SCD-LDD provides one more degree of freedom in optimizing the n- region doping profiles as a new LATID structure.