Browsing by Author "CHOU, PC"

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A NEW APPROACH TO MODELING THE SUBSTRATE CURRENT OF PRESTRESSED AND POST-STRESSED MOSFETS
(1995-06-01)
YANG, JJ
;
SHAOSHIUN, S
;
CHOU, PC
;
CHEN, CH
;
LIN, MS
In this paper, we propose a closed form expression of a new and accurate analytical substrate current model for both pre-stressed and post-stressed MOSFET's, It was derived based on the concept of effective electric field, which gives a more reasonable impact ionization rate in the lucky-electron model, This effective electric field, composed by two experimentally determined parameters, ran be regarded as a result of nonlocal heating effects within de,ices, This model shows a significant improvement to the conventional local field model. One salient feature of the present model is that it allows us to characterize the time evolution of the substrate current of stressed MOSFET's for the first time. Experimental verification for a wide variety of MOSFET's with effective channel lengths down to 0.3 mu m shows that the new model is very accurate and is feasible for any kind of MOS device with different drain structures, The present model can be applied to explore the hot carrier effect in designing submicrometer MOS devices with emphasis on the design optimization of a device drain engineering issue, In addition, the present model is well suited for device reliability analysis and circuit level simulations.
EFFECTS OF HOT-CARRIER-INDUCED INTERFACE STATE GENERATION IN SUBMICRON LDD MOSFETS
(1994-09-01)
WANG, TH
;
HUANG, CM
;
CHOU, PC
;
CHUNG, SSS
;
CHANG, TE
A two-dimensional numerical simulation including a new interface state generation model has been developed to study the performance variation of a LDD MOSFET after a dc voltage stress. The spatial distribution of hot carrier induced interface states is calculated with a breaking silicon-hydrogen bond model. Mobility degradation and reduction of conduction charge due to interface traps are considered. A 0.6 mum LDD MOSFET was fabricated. The drain current degradation and the substrate current variation after a stress were characterized to compare the simulation. A reduction of the substrate current at V(g) congruent-to 0.5 V(d) in a stressed device was observed from both the measurement and the simulation. Our study reveals that the reduction is attributed to a distance between a maximum channel electric field and generated interface states.