Browsing by Author "CHUANG Ching-Te"

Now showing 1 - 4 of 4

CONTROL CIRCUIT OF SRAM AND OPERATING METHOD THEREOF
(2014-03-06)
CHUANG Ching-Te
;
LIEN Nan-Chun
;
LIAO Wei-Nan
;
CHU Li-Wei
;
CHANG Chi-Shin
A control circuit of SRAM and an operating method thereof are provided. The control circuit includes a memory array, a word-line driver, a boost circuit and a voltage level detecting circuit. The memory array includes a plurality of memory cells. Each memory cell includes a plurality of transistors. The word-line driver is to activate the word-line of the memory array for cell storage data access. The boost circuit is to provide the higher voltage source for the word-line driver and a first operating voltage for boosting the first operating voltage to a second operating voltage. The voltage level detecting circuit is detecting if the first operation voltage needed boosted with boost-operation and a detecting-trigger signal and controls the operating of the boost circuit based on the detecting-trigger signal, the first operating voltage and a predetermined voltage.
INDEPENDENTY-CONTROLLED-GATE SRAM
(2013-04-25)
CHUANG Ching-Te
;
Chen Yin-Nien
;
Hsieh Chien-Yu
;
Fan Ming-Long
;
Hu Pi-Ho
The present invention provides an IG 7T FinFET SRAM, which adopts independently-controlled-gate super-high-VT FinFETs to achieve a stacking-like property, whereby to eliminate the read disturb and half-select disturb. Further, the present invention uses keeper circuits and read control voltage to reduce leakage current of the bit lines during read. Furthermore, the present invention can effectively overcome the problem of the conventional 6T SRAM that is likely to have read errors at low operation voltage.
SRAM based on 6 transistor structure including a first inverter, a second inverter, a first pass-gate transistor, and a second pass-gate transistor
(2013-08-29)
CHUANG Ching-Te
;
Jou Shyh-Jye
;
Hwang Wei
;
Lin Yi-Wei
;
Tsai Ming-Chien
The present invention provides a 6T SRAM including a first inverter, a second inverter, a first pass-gate transistor, and a second pass-gate transistor. The first inverter zs a first pull-up transistor and a first pull-down transistor. The second inverter includes a second pull-up transistor and a second pull-down transistor. The gate of the second pull-up transistor is coupled with the gate of the second pull-down transistor, and the drain of the second pull-up transistor is coupled with the drain of the second pull-down transistor. The SRAM can measure the trip voltage, the read disturb voltage, and the write margin by controlling the first bit line, the second bit line, the GND, the first word line, and the voltage source without changing of the physic parameter of the SRAM.
STATIC RANDOM ACCESS MEMORY WITH RIPPLE BIT LINES/SEARCH LINES FOR IMROVING CURRENT LEAKAGE/VARIATION TOLERANCE AND DENSITY/PERFORMANCE
(2014-03-20)
CHUANG Ching-Te
;
YANG Hao-I
;
LU Chien-Yu
;
CHEN Chien-Hen
;
CHANG Chi-Shin
A static random access memory includes a pre-charger, a first cell column array/peripheral circuit, and a first ripple buffer. The pre-charger is connected to a first local bit line in order to pre-charge the first local bit line. The first cell column array/peripheral circuit is connected to the first local bit line and has a plurality of cells for temporarily storing data. The cells are connected to the first local bit line. The first ripple buffer is connected to the first local bit line and a second local bit line in order to send the data from the first local bit line to the second local bit line.