Browsing by Author "CHUNG, SSS"

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A CHARGE-BASED CAPACITANCE MODEL OF SHORT-CHANNEL MOSFETS
(1989-01-01)
CHUNG, SSS
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A COMPLETE MODEL OF THE IV CHARACTERISTICS FOR NARROW-GATE MOSFETS
(1990-04-01)
CHUNG, SSS
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A NEW APPROACH TO DETERMINE THE DRAIN-AND-SOURCE SERIES RESISTANCE OF LDD MOSFETS
(1993-09-01)
CHUNG, SSS
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LEE, JS
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new method for determining the intrinsic drain-and-source series resistance and the effective channel length of LDD MOSFET's is proposed. The method is based on the experimentally measured device I-V characteristics and a new parameter extraction procedure. A consistent set of the effective channel length and the gate-voltage-dependent drain-and-source series resistance was thus determined. The comparison between the measured and experimental drain current characteristics shows excellent agreement using the present model values.
A UNIFIED 3-D MOBILITY MODEL FOR THE SIMULATION OF SUBMICRON MOS DEVICES
(1993-04-01)
YANG, JJ
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CHUNG, SSS
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CHANG, CH
;
LEE, GH
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電子工程學系及電子研究所
A calibrated and physically based mobility model is developed for three-dimensional simulation of submicron metal-oxide-semiconductor (MOS) devices, in which the inversion layer mobility is emphasized. This inversion layer mobility can be generalized into a local form, i.e., expressed as functions of the local electric field at each grid point, so that it is well suited for device simulation. The resulting 3-D mobility model accurately characterizes the significant physical scattering effects including the Coulomb screening effect, quantum channel broadening effect, surface roughness scattering, structure-induced lateral surface scattering and velocity saturation limited effects. Results show that this new model can be incorporated into device simulators for accurately predicting drain currents of submicron LDD MOS devices. Moreover, the results compare more favorably with the experimental data than do those for other reported models.
AN ANALYTICAL THRESHOLD-VOLTAGE MODEL OF TRENCH-ISOLATED MOS DEVICES WITH NONUNIFORMLY DOPED SUBSTRATES
(1992-03-01)
CHUNG, SSS
;
LI, TC
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A simple closed-form expression of the threshold voltage is developed for Trench-Isolated MOS (TIMOS) devices with feature size down to the deep-submicrometer range. The analytical expression is the first developed to include the non-uniform doping effect of a narrow-gate-width device. The inverse narrow width effect can be predicted analytically from the proposed model. It was derived by modeling the gate sidewall capacitance to include the two-dimensional field-induced edge fringing effect and solving the Poisson equation to include the channel implant effect at different operating backgate biases. A two-dimensional simulation program was also developed, and the simulated data were used for verification of the analytical model. Good agreements between the modeled and simulated data have been achieved for a wide range of gate widths and biases. The model is well suited for the design of the basic transistor cell in DRAM circuits using trench field oxide isolation structure.
AN EFFICIENT SEMI-EMPIRICAL MODEL OF THE IV CHARACTERISTICS FOR LDD MOSFETS
(1989-09-01)
CHUNG, SSS
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LIN, TS
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CHEN, YG
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
DIRECT OBSERVATION OF CHANNEL-DOPING-DEPENDENT REVERSE SHORT-CHANNEL EFFECT USING DECOUPLED C-V TECHNIQUE
(1994-01-01)
GUO, JC
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HSU, CCH
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CHUNG, SSS
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電控工程研究所
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Institute of Electrical and Control Engineering
A non-destructive high resolution ''Decoupled C-V Technique'' for small geometry devices has been developed and demonstrated to successfully extract the intrinsic channel capacitance of submicron metal-oxide-semiconductor field effect transistors (MOSFET's). The effective channel doping concentration calculated from the extracted intrinsic gate capacitance presents an obvious dopant concentration enhancement in the intrinsic channel region of submicron devices compared to that of long channel devices, as the channel implant dose increases beyond a critical value. The anomalous reverse short channel effect i.e. threshold voltage increases with channel length scaled down, is simultaneously observed on the heavily doped short channel devices. The self-consistency between the C-V and I-V measurement supports that the reverse short channel effect apparent in the submicron CMOS technology is due to the channel dopant enhancement induced by high dose channel implants for both N-channel and P-channel devices.
EFFECTS OF HOT-CARRIER-INDUCED INTERFACE STATE GENERATION IN SUBMICRON LDD MOSFETS
(1994-09-01)
WANG, TH
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HUANG, CM
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CHOU, PC
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CHUNG, SSS
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CHANG, TE
A two-dimensional numerical simulation including a new interface state generation model has been developed to study the performance variation of a LDD MOSFET after a dc voltage stress. The spatial distribution of hot carrier induced interface states is calculated with a breaking silicon-hydrogen bond model. Mobility degradation and reduction of conduction charge due to interface traps are considered. A 0.6 mum LDD MOSFET was fabricated. The drain current degradation and the substrate current variation after a stress were characterized to compare the simulation. A reduction of the substrate current at V(g) congruent-to 0.5 V(d) in a stressed device was observed from both the measurement and the simulation. Our study reveals that the reduction is attributed to a distance between a maximum channel electric field and generated interface states.
TRANSCONDUCTANCE ENHANCEMENT DUE TO BACK BIAS FOR SUBMICRON NMOSFET
(1995-02-01)
GUO, JC
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CHANG, MC
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LU, CY
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HSU, CCH
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CHUNG, SSS
For the first time, a new phenomenon of transconductance enhancement due to back bias found in submicron MOSFET's is reported. A two-dimensional numerical simulation has been performed to investigate the origin of this observation. The enhancement of the channel potential gradient is verified to be the main reason responsible for this anomalous transconductance enhancement effect. Moderate channel doping concentrations (5 x 10(16) similar to 5 x 10(17) cm(-3)), short channel lengths (submicron regime), and operation under small drain bias are three key conditions for the maximum transconductance enhancement due to the back bias to occur. A conventional linear I-V model, which employs an effective channel length defined by the source/drain metallurgical junctions and bias-independent source/drain extrinsic resistance is not able to predict such characteristics.