Browsing by Author "Cauwenberghs, Gert"

Now showing 1 - 4 of 4

A brain-machine interface using dry-contact, low-noise EEG sensors
(2008-01-01)
Sullivan, Thomas J.
;
Deiss, Stephen R.
;
Jung, Tzyy-Ping
;
Cauwenberghs, Gert
;
交大名義發表
Electroencephalograph (EEG) recording systems offer a versatile, non-invasive window on the brain's spatiotemporal activity for many neuroscience and clinical applications. Our research aims to improve the convenience and mobility of EEG recording by eliminating the need for conductive gel and creating sensors that fit into a scalable array architecture. The EEG dry-contact electrodes are created with micro-electrical-mechanical system (MEMS) technology. Each channel of our analog signal processing front-end comes on a custom-built, dime-sized circuit board which contains an amplifier, filters, and analog-to-digital conversion. A daisy-chain configuration between boards with bit-serial output reduces the wiring needed. A system consisting of seven sensors is demonstrated in a real-world setting. Consuming just 3 mW, it is suitable for mobile applications. The system achieves an input-referred noise of 0.28 mu V-rms in the signal band of 1 to 100 Hz, comparable to the best medical-grade systems in use. Noise behavior across the daisy-chain is characterized, alpha-band rhythms are detected, and an eye-blink study is demonstrated.
An Effective Chip Implementation of A Real-time Eight-channel EEG Signal Processor Based on On-line Recursive ICA Algorithm
(2012)
Shih, Wei-Yeh
;
Huang, Kuan-Ju
;
Chen, Chiu-Kuo
;
Fang, Wai-Chi
;
Cauwenberghs, Gert
This paper presents an effective chip implementation of a real-time eight-channel electroencephalogram signal processor based on on-line recursive independent component analysis (ORICA) algorithm. The system architecture is composed of a memory unit, a whitening unit, an ORICA training unit, and an ORICA computation unit. The proposed architecture is implemented using TSMC 90 nm CMOS technology. It occupies a core area of 800x800 mu m(2) and consumes 4.18 mW at a core supply voltage of 1.0 V and 50 MHz clock operating frequency. Simulated super and sub-Gaussian signals are used to verify the system. The separated signals match those obtained using off-line Matlab-based analysis.
An Efficient ASIC Implementation of 16-channel On-line Recursive ICA Processor for Real-time EEG System
(2014-01-01)
Fang, Wai-Chi
;
Huang, Kuan-Ju
;
Chou, Chia-Ching
;
Chang, Jui-Chung
;
Cauwenberghs, Gert
This is a proposal for an efficient very-large-scale integration (VLSI) design, 16-channel on-line recursive independent component analysis (ORICA) processor ASIC for real-time EEG system, implemented with TSMC 40 nm CMOS technology. ORICA is appropriate to be used in real-time EEG system to separate artifacts because of its highly efficient and real-time process features. The proposed ORICA processor is composed of an ORICA processing unit and a singular value decomposition (SVD) processing unit. Compared with previous work [1], this proposed ORICA processor has enhanced effectiveness and reduced hardware complexity by utilizing a deeper pipeline architecture, shared arithmetic processing unit, and shared registers. The 16-channel random signals which contain 8-channel super-Gaussian and 8-channel sub-Gaussian components are used to analyze the dependence of the source components, and the average correlation coefficient is 0.95452 between the original source signals and extracted ORICA signals. Finally, the proposed ORICA processor ASIC is implemented with TSMC 40 nm CMOS technology, and it consumes 15.72 mW at 100 MHz operating frequency.
An Efficient VLSI Implementation of On-line Recursive ICA Processor for Real-time Multi-channel EEG Signal Separation
(2013)
Shih, Wei-Yeh
;
Liao, Jui-Chieh
;
Huang, Kuan-Ju
;
Fang, Wai-Chi
;
Cauwenberghs, Gert
This paper presents an efficient VLSI implementation of on-line recursive ICA (ORICA) processor for real-time multi-channel EEG signal separation. The proposed design contains a system control unit, a whitening unit, a singular value decomposition unit, a floating matrix multiply unit and, and an ORICA weight training unit. Because the input sample rate of the ORICA processor is 128 Hz, the ORICA processor should produce independent components before the next sample is input in 1/128 s. Under the timing constraints of commutating multi-channel ORICA in real time, the design of the ORICA processor is a mixed architecture, which is designed as different hardware parallelism according to the complexity of processing units. The shared arithmetic processing unit and shared register can reduce hardware complexity and power consumption. The proposed design is implemented used TSMC 90nm CMOS technology with 8-channel EEG processing in 128 Hz sample rate of raw data and consumes 2.827 mW at 50 MHz clock rate. The performance of the proposed design is also shown to reach 0.0078125 s latency after each EEG sample time, and the average correlation coefficient between the original source signals and extracted ORICA signals for each 1s frame is 0.9763.