Browsing by Author "Chan, Chia-Kai"

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FFT-Based Multirate Signal Processing for 18-Band Quasi-ANSI S1.11 1/3-Octave Filter Bank
(2019-05-01)
Liu, Chih-Wei
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Chan, Chia-Kai
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Cheng, Po-Hsiang
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Lin, Hsin-Yuan
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電子工程學系及電子研究所
For characteristic analysis of the 24 KHz audio, the 10-ms, 18-band quasi-ANSI filter bank has been proposed and designed for advanced hearing aids. To greatly reduce the computation complexity, several time-domain multirate signal processing techniques, such as the up-and down-sampling rate conversions and the interpolated finite impulse response (IFIR) filters, were investigated. However, it is well known that using fast Fourier transform (FFT) to perform the linear convolution can dramatically reduce the computational complexity. Taking both advantages, in this brief we investigated the FFT-based multirate signal-processing technique and explored their efficient architecture. To demonstrate the success of the proposed architecture, we implemented a real-valued FFT-based 10.7-ms, 18-band quasi-ANSI 1/3-octave filter bank using TSMC 90-nm CMOS high-VT technology. We found that, for each input sample, the proposed FFT-based quasi-ANSI 1/3-octave filter bank used approximately 77% fewer multiplications than the previous time-domain design. The proposed FFT-based quasi-ANSI filter bank was operated at 13 MHz to process the 24-KHz audio in real time, and it consumed only 14 mu W (@0.9V) of dynamic power.
High-Throughput 64K-point FFT Processor for THz Imaging Radar System
(2019-01-01)
Chan, Chia-Kai
;
Lin, Hong-Ke
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Liu, Chih-Wei
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Radar technology and its developments have been important issues for decades. With the growth of semiconductor processing technology, the development of circuit design related to THz technology has gradually been noted such as imaging radar system. However, there are ultra-long series in the application of wideband radar system with high sampling rate. While realizing the ultra-long FFT, it would introduce some design challenges. On the other hand, it needs to achieve a high throughput rate to meet the requirement of real-time processing. In this paper, we implement a 4-parallel 64K-point FFT hardware architecture based on 2-epoch FFT algorithm. With the proposed middle twiddle factor generator, we can reduce a large number of storages for twiddle factor coefficients, so that the area of ROM can be reduced. We implement this work in TSMC 90 nm CMOS technology with high-Vt standard cell library and the total gate counts are around 3974.1k. The maximum operating frequency of the system is 390 MHz. When operating at the maximum operating frequency, the throughput reaches 1.57 GS/s and it consumes 0.2811 W @0.9 V).