Browsing by Author "Chan, Ching-Da"

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A Digital Golay-MPIC Time Domain Equalizer for SC/OFDM Dual-Modes at 60 GHz Band
(2013-10-01)
Liu, Wei-Chang
;
Yeh, Fu-Chun
;
Wei, Ting-Chen
;
Chan, Ching-Da
;
Jou, Shyh-Jye
In this paper, a digital time domain equalizer (TDE) for 60 GHz radio frequency transmission systems is presented. Significantly, the TDE supports both single carrier (SC) and orthogonal frequency-division multiplexing (OFDM) operation modes for digital baseband receiver. In order to improve the performance, the proposed TDE adopts Golay sequence aided one-shot channel estimation and modified multi-path interference cancellation (MPIC) equalization. Targeting on the line-of-sight (LOS) channel characteristic, MPIC is simplified with single-tap for complexity reduction. From the area efficiency point of view, both SC and OFDM modes are designed within a single hardware to yield 99% of area sharing. The Golay-MPIC TDE structure is realized as feed-forward data path with 8X-parallelism to achieve 2.64 GS/s at 330 MHz clock rate. The Golay-MPIC TDE is fabricated as a part of a digital baseband with 65 nm 1P9M general purpose process. The area of Golay-MPIC TDE occupies 1.05 with 405 K gate counts. Besides, the power dissipations for SC and ODFM modes are 56.71 mW@220 MHz (1 V) and 91.29 mW@330 MHz (1.1 V), respectively. Finally, the chip can provide the maximum throughput 15.84 Gb/s (2.64 GS/s with 64-QAM modulation).
A SC/HSI Dual-Mode Baseband Receiver with Frequency-Domain Equalizer for IEEE 802.15.3c
(2013)
Liu, Wei-Chang
;
Yeh, Fu-Chun
;
Wei, Ting-Chen
;
Huang, Ya-Shiue
;
Liu, Tai-Yang
In this paper, an 8X-parallelism digital baseband receiver is proposed for IEEE 802.15.3c application. The baseband receiver consists of all-digital synchronization, radix-16 FFT and LS-LMS equalizer modules. It supports SC and HSI dual-mode in IEEE 802.15.3c with single hardware for area efficiency. The chip is implemented with 65 nm 1P9M process. The fabricated area is 12.96 mm(2) with 3463 K gate counts. The post-layout verification shows the throughput rate under QPSK modulation achieves 3.52 Gb/s and 5.28 Gb/s for SC mode (220 MHz) and HSI mode (330 MHz), respectively.
All-Digital Synchronization for SC/OFDM Mode of IEEE 802.15.3c and IEEE 802.11ad
(2015-02-01)
Liu, Wei-Chang
;
Wei, Ting-Chen
;
Huang, Ya-Shiue
;
Chan, Ching-Da
;
Jou, Shyh-Jye
In this paper, a detection and estimation scheme and its architecture design for synchronization in 60 GHz indoor wireless transmission are presented. With the complementary Golay sequence based preamble structure, the proposed synchronization scheme is designed to detect the preamble and symbol boundary, estimate the frequency offset within a unified architecture. For the very high sampling speed at 60 GHz transmission, the architecture is designed as 8x-parallelism with feed-forward data path. This architecture supports the single carrier (SC) and orthogonal frequency-division multiplexing (OFDM) transmissions of both IEEE 802.15.3c and IEEE 802.11ad standards. The synchronization module is implemented as a part of a digital baseband receiver for IEEE 802.15.3c. The tolerance of maximum frequency offset is about 114.58 ppm and 171.87 ppm for SC and OFDM mode, respectively. The implementation result shows that it takes about 0.84 mm(2) of area (equivalent to 307 k gate counts). The power consumption is about 59 mW in SC mode and 96 mW in OFDM (HSI) mode when operating at 1.76 GHz and 2.64 GHz chip rate, respectively.
An IEEE 802.15.3c/802.11ad Compliant SC/OFDM Dual-Mode Baseband Receiver for 60 GHz Band
(2014-01-01)
Liu, Wei-Chang
;
Yeh, Fu-Chun
;
Wu, Chia-Yi
;
Wei, Ting-Chen
;
Huang, Ya-Shiue
In this paper, a dual-standard, dual-mode baseband receiver for 60 GHz wireless communication is presented. The receiver is designed to support SC and OFDM modes for both IEEE 802.15.3c and IEEE 802.11ad standards. The receiver is integrated with all-digital synchronization, radix-16 FFT, phase noise cancellation and low-complexity time-domain equalizer for line-of-sight channel application. The hardware utilization achieves 70% by leveraging hardware sharing between two modes and two standards for area efficiency. The receiver is implemented with 65 nm 1P9M process in 7.95 mm(2) core area. With feed-through architecture, the throughput rate supports up to 7.04 Gb/s and 15.84 Gb/s for SC mode (220 MHz) and OFDM mode (330 MHz), respectively.
ERROR-RESILIENT SEQUENTIAL CELLS WITH SUCCESSIVE TIME BORROWING FOR STOCHASTIC COMPUTING
(2016)
Liu, Wei-Chang
;
Chan, Ching-Da
;
Huang, Shuo-An
;
Lo, Chi-Wei
;
Yang, Chia-Hsiang
This paper presents error-resilient sequential building blocks with time-borrowing capability without extra latches and generated clocks. The circuits are able to recover the timing errors caused by PVT variations and/or over-voltage scaling by up to half a cycle. Unlike prior works, the timing errors can be recovered dynamically through successive time borrowing without stalled cycles, retaining a constant throughput. The circuit structure can be applied to both ASICs and microprocessors. The proposed sequential cells are highly compatible with current cell-based IC design flow, for both feed-forward and feedback datapaths. As a proof of concept, a design with key DSP building blocks has been verified. The results show that the performance of the DSP modules is improved by 13-15% in the worst-case operation condition, yielding a promising solution for stochastic computing under an unreliable operation condition.
Power and Area Reduction in Multi-Stage Addition Using Operand Segmentation
(2013-01-01)
Chan, Ching-Da
;
Liu, Wei-Chang
;
Yang, Chia-Hsiang
;
Jou, Shyh-Jye
;
電子工程學系及電子研究所
This paper presents an architectural technique to efficiently implement multi-stage additions through operand segmentation. Carry bypass is leveraged to break the dependency between the two segmented adders, reducing the delay of the critical path. This allows for power-and area-efficient hardware implementation due to the increased timing margin for architectural transformations at the cost of one extra clock cycle. Compared to existing segmented-adders, the proposed architecture has the least hardware overhead with near execution time. An accumulator and a 16-tap FIR filter are used to demonstrate the delay, power, and area improvements of the proposed technique. The synthesis results show that the delay is improved by up to 42% and 28.1%. Gi ven the same timing constraint, the adder area is reduced by 27.4% and 12.4%.
Power and Area Reduction in Multi-Stage Addition Using Operand Segmentation
(2013)
Chan, Ching-Da
;
Liu, Wei-Chang
;
Yang, Chia-Hsiang
;
Jou, Shyh-Jye
;
電子工程學系及電子研究所
This paper presents an architectural technique to efficiently implement multi-stage additions through operand segmentation. Carry bypass is leveraged to break the dependency between the two segmented adders, reducing the delay of the critical path. This allows for power-and area-efficient hardware implementation due to the increased timing margin for architectural transformations at the cost of one extra clock cycle. Compared to existing segmented-adders, the proposed architecture has the least hardware overhead with near execution time. An accumulator and a 16-tap FIR filter are used to demonstrate the delay, power, and area improvements of the proposed technique. The synthesis results show that the delay is improved by up to 42% and 28.1%. Given the same timing constraint, the adder area is reduced by 27.4% and 12.4%.