Browsing by Author "Chan, Hsun-Wei"

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A 75-Gb/s/mm(2) and Energy-Efficient LDPC Decoder Based on a Reduced Complexity Second Minimum Approximation Min-Sum Algorithm
(2020-04-01)
Lopez, Henry
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Chan, Hsun-Wei
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Chiu, Kang-Lun
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Tsai, Pei-Yun
;
Jou, Shyh-Jye Jerry
This article presents a high-throughput and low-routing complexity low-density parity check (LDPC) decoder design based on a novel second minimum approximation min-sum (SAMS) algorithm. The routing congestion is mitigated by reducing the required interconnections in the critical path of the routing network. The implementation and postlayout results with 28-nm 1P9M CMOS process show that the proposed design can achieve a throughput of 10.5 Gb/s for a millimeter-wave 60-GHz baseband system while satisfying the low bit error rate (BER) requirements (10(-7)). The proposed design reduces the wiring in the routing network by 21% and improves the area by 12% compared to the conventional min-sum (MS) and normalized MS (NMS) algorithm. Additional hardware optimizations are obtained by considering the internal message passing resolution based on the BER and signal-to-noise ratio (SNR) requirements for a practical baseband system. The power consumption is efficiently reduced by the employment of a shared address generator that exploits the degree of parallelism to reduce the switching activity on a group of memory elements. The LDPC decoder is implemented with a core area of 0.14 mm(2), power consumption of 81 mW at 312.5 MHz, and the area and power efficiency of 75 Gb/s/mm(2) and 10.2 pJ/bit, respectively.
A Millimeter Wave Digital CMOS Baseband Transceiver for Wireless LAN Applications
(2019-01-01)
Chiu, Kang-Lun
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Chan, Hsun-Wei
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Lee, Wei-Che
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Wu, Chang-Ting
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Lopez, Henry
In this paper, we introduce a 10 Gbps digital baseband transceiver with IV supply voltage, 16-QAM, 3/4 code rate single carrier mode using 28 nm CMOS process to do the implementation. In millimeter wave communications, well-defined standard, IEEE 802.11ad is referenced for our system design and simulation. We target at modified chip rate 2.5 GHz with 4 times parallelism hardware at clock rate 625 MHz. The overall transceiver architecture design with hardware implementation considerations will be proposed. With the smart shared memory allocation, we can reduce 31% of the total amount. According to the referenced specifications, we achieve the required bit error rate 3 x 10(-7) before SNR 18.5 dB. After the system algorithm design, we implement the hardware with the core area 2.92 mm(2) with measured power 1.8 Watt for baseband transceiver chip. The performance of energ,y per bit is 0.023 nJ and 0.211 nJ per hit 6w Tx and Rx, including ADC/DAC.
A Pseudo MMSE Linear Equalizer for 60GHz Single Carrier Baseband Receiver
(2017-01-01)
Chan, Hsun-Wei
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Wu, Chang-Ting
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Jen, Chih-Wei
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Liu, Chun-Yi
;
Lee, Wei-Che
In this paper, a pseudo minimum mean square error (P-MMSE) frequency domain equalizer (FDE) is proposed to combat deep fading channel for single carrier (SC) modulation under IEEE 802.11ad and IEEE 802.15.3c standard. This FDE has resistance like MMSE to deep fading channel and maintain low complexity like zero-forcing (ZF) equalizer. In order to calculate bit error rate (BER) performance, the proposed P-MMSE integrating with our previous dual-mode baseband receiver [1] to do simulation. P-MMSE FDE can provide about 1dB improvement for 16QAM and 5 dB improvement for QPSK and BPSK when BER at 10(-2) in serious deep fading channel. Besides, it enhances the BER floor from 4 x 10(-3) to 10(-3) in 16-QAM. Moreover, P-MMSE FDE maintains the same complexity as ZF FDE.
Digital Self-Interference Cancellation for OFDM Full-Duplex Transmission in 60 GHz Band
(2018-01-01)
Jen, Chih-Wei
;
Yang, Hung-Wei
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Chan, Hsun-Wei
;
Liu, Hung-Chih
;
Lopez, Henry
In this paper, we proposed an all-digital selfinterference cancellation (DSIC) with correction vector for convolution (CVC) technique to eliminate serious multipath self-interference for orthogonal frequency-division multiplexing (OFDM) full-duplex transmission in 60 GHz band. The CVC can solve the non-equivalence of circular and linear convolution. This work based on IEEE 802.15.3c/IEEE 802.11ad specification is synthesized with 40 nm 1P9M general purposes process. Under the Access Point (AP) and the User Equipment (UE) horn antennas being aligned face to face, the 9-bit fixed-point simulation result shows the proposed technique can achieve the target of the uncoded bit-error-rate (BER) of 10-2 at signal-to-noise ratio (SNR) of 24.8 dB satisfying the requirement of 26 dB.