Browsing by Author "Chang, CY"

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2 V-operated InGaP-AlGaAs-InGaAs enhancement-mode pseudomorphic HEMT
(2005-02-01)
Chu, LH
;
Chang, EY
;
Chen, SH
;
Lien, YC
;
Chang, CY
A low-voltage single power supply enhancement-mode InGaP-AlGaAs-InGaAs pseudomorphic high-electron mobility transistor (PHEMT) is reported for the first time. The fabricated 0.5 x 160 mum(2) device shows low knee voltage of 0.3 V, drain-source current (I-DS) of 375 mA/mm and maximum transconductance of 550 mS/mm when drain-source voltage (V-DS) was 2.5 V. High-frequency performance was also achieved; the cut-off frequency(F-t) is 60 GHz and maximum oscillation frequency(F-max) is 128 GHz. The noise figure of the 160-mum gate width device at 17 GHz was measured to be 1.02 dB with 10.12 dB associated gain. The E-mode InGaP-AlGaAs-InGaAs PHEMT, exhibits a high output power density of 453 mW/mm with a high linear gain of 30.5 dB at 2.4 GHz. The E-mode PHEMT can also achieve a high maximum power added efficiency (PAE) of 70%, when tuned for maximum PAE.
2-bit poly-Si-TFT nonvolatile memory using hafnium oxide, hafnium silicate and zirconium silicate
(2005)
Lin, YH
;
Chien, CH
;
Chou, TH
;
Chao, TS
;
Chang, CY
In this paper, we, for the first time, have successfully fabricated SONOS-type poly-Si-TFT memories employing three kinds of high-k dielectrics, including HfO(2), Hf-silicate and Zr-silicate, as the trapping layer with low-thermal budget processing. It was demonstrated that the fabricated memories exhibit good performance in terms of relatively large memory window, high program/erase speed (1ms/10ms), long retention time (> 10(6)S for 20% charge loss) and negligible read/write disturbances. In particular, 2-bit operation has been successfully demonstrated.
2-V-operation delta-doped power HEMT's for personal handy-phone systems
(1997-08-01)
Lai, YL
;
Chang, EY
;
Chang, CY
;
Liu, TH
;
Wang, SP
A high-efficiency and high-power-density delta-doped AIGaAs/InGaAs HEMT with low adjacent channel leakage has been developed for the digital wireless personal handy-phone system (PHS). When qualified by 1.9-GHz pi/4-shifted quadrature phase shift keying (QPSK) modulated PHS standard signals, the 2.0-V-operation HEMT with a 1-mm gate width demonstrated a power-added efficiency of 45.3% and an output power density of 105 mW/mm. This is the highest power density ever reported by the power transistors for the PHS. The state-of-the-art results for the PHS operating at 2.0 V were achieved by the delta-doped power HEMT for the first time.
2-V-operation delta-doped power HEMT's for personal handy-phone systems
(1997-08-01)
Lai, YL
;
Chang, EY
;
Chang, CY
;
Liu, TH
;
Wang, SP
A high-efficiency and high-power-density delta-doped AIGaAs/InGaAs HEMT with low adjacent channel leakage has been developed for the digital wireless personal handy-phone system (PHS). When qualified by 1.9-GHz pi/4-shifted quadrature phase shift keying (QPSK) modulated PHS standard signals, the 2.0-V-operation HEMT with a 1-mm gate width demonstrated a power-added efficiency of 45.3% and an output power density of 105 mW/mm. This is the highest power density ever reported by the power transistors for the PHS. The state-of-the-art results for the PHS operating at 2.0 V were achieved by the delta-doped power HEMT for the first time.
5 mm high-power-density dual-delta-doped power HEMT's for 3 V L-band applications
(1996-05-01)
Lai, YL
;
Chang, EY
;
Chang, CY
;
Chen, TK
;
Liu, TH
A high-power-density dual-delta-doped AlGaAs/InGaAs/GaAs high electron mobility transistor (HEMT) for personal communication applications has been developed. A 5.0 mm gate-width device operating at a drain bias of 3.0 V gave an output power over 1 W, The 1 mu m gate-length HEMT exhibited a current density of 425 mA/mm at V-gs = 0.5 V, The maximum transconductance of the device was 270 mS/mm, The effective knee voltage was as low as 0.3 V, At the class AB operation, the HEMT demonstrated an output power density of 200 mW/mm, 64% power-added efficiency and 18.2 dB linear gain at 900 MHz, This is the highest power density of a dual-delta-doped AlGaAs/InGaAs/GaAs HEMT reported to date for low voltage (3 V) wireless applications.
5 mm high-power-density dual-delta-doped power HEMT's for 3 V L-band applications
(1996-05-01)
Lai, YL
;
Chang, EY
;
Chang, CY
;
Chen, TK
;
Liu, TH
A high-power-density dual-delta-doped AlGaAs/InGaAs/GaAs high electron mobility transistor (HEMT) for personal communication applications has been developed. A 5.0 mm gate-width device operating at a drain bias of 3.0 V gave an output power over 1 W, The 1 mu m gate-length HEMT exhibited a current density of 425 mA/mm at V-gs = 0.5 V, The maximum transconductance of the device was 270 mS/mm, The effective knee voltage was as low as 0.3 V, At the class AB operation, the HEMT demonstrated an output power density of 200 mW/mm, 64% power-added efficiency and 18.2 dB linear gain at 900 MHz, This is the highest power density of a dual-delta-doped AlGaAs/InGaAs/GaAs HEMT reported to date for low voltage (3 V) wireless applications.
A broadband and low cost monolithic BiCMOS tuner chip
(2004-11-01)
Chen, YH
;
Cheng, TY
;
Chang, CY
;
交大名義發表
;
National Chiao Tung University
This circuit is a single chip of a BiCMOS wafer used in cable TV set-top converters;, cable modems, cable TV tuners and digital TVs. It is a double conversion tuner (DCT) structure which has better performance characteristics than the single conversion tuner (SCT). This single chip comprises two LNAs, one AGC, two LO buffers, two VCOs, two resistor-type and double-balanced Gilbert cell mixers, two synthesizers and ESD protection. Its total gain is 45.70 dB, and its total noise figure is 4.3-7.9 dB. The RF varied range, which is not only 50-860 MHz but also 50-1000 MHz, can be applied in cable TV tuners and cable modems. The consuming power is 0.885 W under 3 V and the die size is 4.8 mm(2).
A CMOS low-noise amplifier for ultra wideband wireless applications
(2005-11-01)
Chou, MF
;
Wuen, WS
;
Wu, CC
;
Wen, KA
;
Chang, CY
A CMOS low noise amplifier (LNA) for low-power ultrawideband (UWB) wireless applications is presented. To achieve low power consumption and wide operating bandwidth, the proposed LNA employing stagger tuning technique consists of two stacked common-source stages with different resonant frequencies. This work is implemented in 0.18-mu m CMOS process and shows a 2.4-9.4-GHz bandwidth. The amplifier provides a maximum forward gain (S-21) of 10.9 dB while drawing 7.1 mW from a 1.8-V supply. A noise figure as low as 4.1 dB and an IIP3 of -3.5 dBm have been demonstrated.
A decade bandwidth resistive FET singly balanced MIC mixer
(1999)
Chang, CY
;
Yang, CC
;
Niu, DC
;
電信工程研究所
;
Institute of Communications Engineering
A novel decade bandwidth resistive FET singly balanced MIC mixer using a broadband CPW to CPS balun is developed. The mixer uses two NEC71000 MESFETs and realized with uniplanar lines. At 17 dBm LO power and 1 GHz IF, the mixer shows a conversion loss of 5.7 to 11 dB for 2 to 20 GHz RF and 10 to 15 dB for 20 to 27 GHz RF. The IF bandwidth is from 10 MHz to 7 GHz. The signal orthogonality between RE and IF makes the IF signal may overlap the RF signal. The mixer shows an output P-1dB of 11.5 dBm (corresponding to input P-1dB of 18.5 dBm) at 8 GHz RF, 1 GHz IF and 16.5 dBm LO power. The input IF, is 24 to 37 dBm corresponding to 2.5 to 20 GHz RF and 1 GHz IF. The mixer is fabricated on a 15 mil thick Al2O3 MIC substrate.
A dual-gate-controlled single-electron transistor using self-aligned polysilicon sidewall spacer gates on silicon-on-insulator nanowire
(2004-03-01)
Hu, SF
;
Wu, YC
;
Sung, CL
;
Chang, CY
;
Huang, TY
A dual-gate-controlled single-electron transistor was fabricated by using self-aligned polysilicon sidewall spacer gates on a silicon-on-insulator nanowire. The quantum dot formed by the electric field effect of the dual-gate structure was miniaturized to smaller than the state-of-the-art feature size, through a combination of electron beam lithography, oxidation, and polysilicon sidewall spacer gate formation processes. The device shows typical MOSFET I-V characteristics at room temperature. However, the Coulomb gap and Coulomb oscillations are clearly observed at 4 K.
A dynamic model of ozone disinfection in a bubble column with oxygen mass transfer
(2002-05-01)
Chen, YH
;
Chang, CY
;
Yu, YH
;
Chiang, PC
;
Chiu, CY
The dynamic process of disinfection with ozone in a bubble column is studied for model establishment. Bubble columns have been widely used for ozone disinfection in plants and laboratories. Ozone is produced by passing oxygen-enriched gas through an ozone generator, and introduced into the bottom of a column equipped with a gas-diffuser. There certainly exists a temporary and unsteady period before the ozone disinfection system reaches steady state. Available ozone disinfection models employed to describe dissolved ozone and surviving microorganism profiles have commonly been developed for steady state. Moreover, oxygen mass transfer has usually been neglected in previous ozone disinfection models. However, this information is desirable for the proper operation of ozone disinfection in a bubble column. Thus, the objective of this study was to model and investigate the dynamic ozone disinfection process in a bubble column with oxygen mass transfer. A dynamic axial dispersion model is proposed and was employed to predict the variation of the ozone, microorganism and oxygen concentrations along the column. The results of prediction were obtained based on the conditions of Marinas et al. (1993). E. coli was chosen as the model microorganism. The dynamic model of ozone inactivation is useful for proper prediction of the variables of an ozone disinfection system in a bubble column.
A GeSi-buffer structure for growth of high-quality GaAs epitaxial layers on a Si substrate
(2005-01-01)
Chang, EY
;
Yang, TH
;
Luo, GL
;
Chang, CY
;
材料科學與工程學系
A SiGe-buffer structure for growth of high-quality GaAs layers on a Si (100) substrate is proposed. For the growth of this SiGe-buffer structure. a 0.8-mum Si-0.1 Ge-0.9 layer was first grown. Because of the large mismatch between this layer and the Si substrate, many dislocations formed near the interface and in the low part of the Si0.1Ge0.9 layer. A 0.8-mum Si0.05Ge0.95 layer and a 1-mum top Ge layer were subsequently grown. The strained Si0.05Ge0.95/Si0.1Ge0.9 and Ge/Si0.05Ge0.95 interfaces formed can bend and terminate the upward-propagated dislocations very effectively. An in-situ annealing process is also performed for each individual layer. Finally, a 1-3-mum GaAs film was grown by metal-organic chemical vapor deposition (MOCVD) at 600degreesC. The experimental results show that the dislocation density in the top Ge and GaAs layers can be greatly reduced, and the surface was kept very smooth after growth, while the total thickness of the structure was only 5.1 mum (2.6-mum SiGe-buffer structure + 29.5-mum GaAs layer).
A high-performance thin-film transistor with a vertical offset structure
(1996-12-01)
Chang, CY
;
Lin, CW
;
交大名義發表
;
電子工程學系及電子研究所
;
National Chiao Tung University
In this study, we propose a novel device structure combined with conventional hydrogenated amorphous silicon (a-Si:H) for the source and drain regions and microcrystalline silicon (mu c-Si:H) for the channel region to obtain a high-performance thin-film transistor (TFT), This is a vertical a-Si:H offset structure used to suppress OFF-state current to a small value which is comparable to the conventional a-Si:H TFT's with a much higher drivability. The fabrication process is simple, low temperature (less than or equal to 300 degrees C), and low cost, with a potential for high reliability.
A high-performance thin-film transistor with a vertical offset structure
(1996-12-01)
Chang, CY
;
Lin, CW
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this study, we propose a novel device structure combined with conventional hydrogenated amorphous silicon (a-Si:H) for the source and drain regions and microcrystalline silicon (mu c-Si:H) for the channel region to obtain a high-performance thin-film transistor (TFT), This is a vertical a-Si:H offset structure used to suppress OFF-state current to a small value which is comparable to the conventional a-Si:H TFT's with a much higher drivability. The fabrication process is simple, low temperature (less than or equal to 300 degrees C), and low cost, with a potential for high reliability.
A macro model of silicon spiral inductor
(2002-05-01)
Su, CY
;
Chen, LP
;
Chang, SJ
;
Tseng, BM
;
Lin, DC
A new automatic parameter extraction method for modeling Of silicon Spiral inductors is presented. The Concepts on self-resonance frequency (f(sr)) and quality factor of a spiral inductor are utilized to develop the concise extraction procedures. In the mean time, the presented extraction procedures are programmed as a macro to execute all the extractions automatically and shorten the extraction time effectively. Without any additional optimization or curve fitting, almost all the patterns of S-parameters between the measured and the simulation of extracted data implemented with the extraction macro are less than 5%. The programmed extraction macro makes it fast and accurate to extract and characterize the behaviours or silicon-based spiral inductors with different structures and substrate resistivities. It provides a concrete foundation commercial silicon radiofrequency (RF) Circuit design to realizing on-chip silicon RF integrated circuits. Furthermore, the directly extracted equivalent model parameters, without an optimization, also provide a rule to fairly, effectively and phsically judge the performance of a spiral inductor. (C) 2002 Elsevier Science Ltd. All rights reserved.
A model for photoresist-induced charging damage in ultra-thin gate oxides
(1997)
Lin, HC
;
Chien, CH
;
Wang, MF
;
Huang, TY
;
Chang, CY
The role of photoresist (PR) in affecting the gate oxide damage during plasma processing boas reexamined in this work. if was observed that, during the O-2 plasma ashing, more severe antenna effect may occur in devices with PR covering. A model is proposed to explain this phenomenon. This model considers the ability of plasma current injection through the substrate contacts, which are hindered by PR covering, to adjust the potential difference between gate electrode and substrate. We Sound that the presence of PR, antenna ratio, and gate-oxide thickness are all important parameters for charging damage effect.
A multilevel interconnect technology with intrametal air gap for high-performance 0.25-mu m-and-beyond devices manufacturing
(1999-11-01)
Lin, M
;
Chang, CY
;
Huang, TY
;
Lin, ML
;
電子工程學系及電子研究所
A multilevel interconnect technology with an intra metal air gap has been developed to reduce the interconnect delay time for versatile. and quick turnaround-time foundry manufacturing. The air-gap method has been successfully applied to 0.25 mu m IC technology and shown to be effective in reducing the parasitic interconnect capacitance. Measurements of various ring oscillators confirm that the smallest delay time is indeed achieved with the air-gap method, compared with other methods using either conventional high-density-plasma (HDP) oxide or low-dielectric-constant spin-on-glass (SOG) as the gap-filling insulating materials. Moreover, the oscillator delay time is found to depend critically on not only the size of the air gap, but also the position of the air gap. Best results in terms of delay time reduction are obtained when the air-gap is positioned in the middle between the two metal lines, and extends both above and below the metal lines to effectively reduce the fringing capacitance. We have also measured the leakage current between adjacent metal lines and confirmed that our new metal intel connect structure with an air gap does not exhibit any appreciable leakage and appears to be suitable For high-performance foundry applications. Lastly, the polarization and thermal characteristics of the air-gap structure were compared with conventional gap-filling methods.
A multioctave bandwidth rat-race singly balanced mixer
(1999-01-01)
Chang, CY
;
Yang, CC
;
Niu, DC
;
傳播研究所
;
Institute of Communication Studies
In this letter, we describe a broad-band 7.5-46 GHz rat-race ring singly balanced mixer. The rat-race ring consists of an ideal crossover phase inverter and is designed to have a Chebyshev response of order two. The mixer diodes are virtually grounded via a quarter-wavelength low-impedance FCPW (finite ground plane CPW) open circuit stubs. The mixer shows more than 5 times RF bandwidth and de to 5 GHz LF bandwidth. The circuit is realized using FCPW on 25 mil Al2O3 substrate.
A new class of wideband multisection 180 degrees hybrid rings using vertically installed planar couplers
(2006-06-01)
Chi, CH
;
Chang, CY
;
電信工程研究所
;
Institute of Communications Engineering
A new class of wideband multisection 180 degrees hybrid rings using the vertically installed planar (VIP) coupler is proposed. On the basis of the reconfigured ideal single-section 180 degrees hybrid ring (i.e., the 180 degrees hybrid ring with an ideal phase inverter), the multisection 180 degrees hybrid rings can be realized by properly cascading of single-section 180 degrees hybrid rings. Compared with the conventional hybrid ring, the two-section hybrid rings exhibit wide bandwidth, size reduction, and easily achievable high power-division ratios. Design equations based on the equal-ripple functions are derived. Design curves for the equal and unequal power-division ratio are also described. In addition, a cascade of single-section cascadable hybrid rings with a unit element at each I/O port can be used for bandwidth enhancement. Good agreement is obtained between the experimental and simulated results.
A new method to extract MOSFET threshold voltage, effective channel length, and channel mobility using S-parameter measurement
(2004-05-01)
Chen, HY
;
Chen, KM
;
Huang, GW
;
Chang, CY
;
Huang, TY
In this work, a simple method for extracting MOSFET threshold voltage, effective channel length and channel mobility by using S-parameter measurement is presented. In the new method, the dependence between the channel conductivity and applied gate voltage of the MOSFET device is cleverly utilized to extract the threshold voltage, while biasing the drain node of the device at zero voltage during measurement. Moreover, the effective channel length and channel mobility can also be obtained with the same measurement. Furthermore, all the physical parameters can be extracted directly on the modeling devices without relying on specifically designed test devices. Most important of all, only one S-parameter measurement is required for each device under test (DUT), making the proposed extraction method promising for automatic measurement applications.