Browsing by Author "Chang, Chang-Hsuan"

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A flexible two-layer external memory management for H.264/AVC decoder
(2007)
Chang, Chang-Hsuan
;
Chang, Ming-Hung
;
Hwang, Wei
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, a flexible two-layer external memory management for H.264/AVC decoder is proposed. Power consumption and data access latency caused by being fetched to/from the off-chip memory greatly affect multimedia system performance. The proposed memory controller consists of two layers. The first layer is the address translation which provides an efficient pixel data arrangement to reduce the row-miss occurrence. The second layer is the external memory interface (EMI) which can further reduce access latency up to 70% by using the specific command FIFO and a unified FSM with generic scheduling. Particularly, the memory utilization can be increased about 3 times as compared with traditional method after combining the address translation layer with external memory interface. Similarly, the proposed memory controller unit is feasible and beneficial for future memory-bandwidth-constraint System-on-Chip applications.
Design of memory sub-system in H.264/AVC decoder
(2007)
Li, Chih-Hung
;
Chang, Chang-Hsuan
;
Peng, Wen-Hsiao
;
Hwang, Wei
;
Chiang, Tihao
In this paper, we present the memory sub-system of a H.264/AVC decoder designed for High profile and Level 4. Our design incorporates a synchronization buffer as a pre-cache buffer. We investigate the efficiency of DRAM access and power dissipation when the buffer is designed at different granularities. Statistical results show that the granularity of larger block size has higher memory efficiency; less access cycles and power dissipation. However, the granularity of 8x8 block size provides better trade-off among cost, efficiency, power, and real-time requirement.