Browsing by Author "Chang, Chi-Min"

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A Novel Test Flow for One-Time-Programming Applications of NROM Technology
(2009)
Chin, Ching-Yu
;
Tsou, Yao-Te
;
Chang, Chi-Min
;
Chao, Mango C. -T.
;
電子工程學系及電子研究所
The NROM technology is an emerging non-volatile-memory technology providing high data density with low fabrication cost. In this paper, we propose a novel test flow for the one-time-programming (OTP) applications using the NROM bit cells. Unlike the conventional test flow, the proposed flow applies the repair analysis in its package testing instead of in its wafer testing, and hence creates a chance for reusing the bit cells originally identified as a defect to represent the value in the OTP application. Thus, the proposed test flow can reduce the number of bit cells to be repaired and further improve the yield. Also, we propose an efficient and effective estimation scheme to predict the probability of a part being successfully repaired before packaged. This estimation can be used to determine whether a part should be packaged, such that the total profit of the proposed test flow can be optimized. A series of experiments are conducted to demonstrate the effectiveness, efficiency, and feasibility of the proposed test flow.
A Novel Test Flow for One-Time-Programming Applications of NROM Technology
(2011-12-01)
Chao, Mango C. -T.
;
Chin, Ching-Yu
;
Tsou, Yao-Te
;
Chang, Chi-Min
;
電子工程學系及電子研究所
The NROM technology is an emerging non-volatile-memory technology providing high data density with low fabrication cost. In this paper, we propose a novel test flow for the one-time-programming (OTP) applications using the NROM bit cells. Unlike the conventional test flow, the proposed flow applies the repair analysis in its package test instead of in its wafer test, and hence creates a chance for reusing the bit cells originally identified as a defect to represent the value in the OTP application. Thus, the proposed test flow can reduce the number of bit cells to be repaired and further improve the yield. Also, we propose an efficient and effective estimation scheme to predict the probability of a part being successfully repaired before packaged. This estimation can be used to determine whether a part should be packaged, such that the total profit of the proposed test flow can be optimized. A series of experiments are conducted to demonstrate the effectiveness, efficiency, and feasibility of the proposed test flow.
Fast Transistor Threshold Voltage Measurement Method for High-Speed, High-Accuracy Advanced Process Characterization
(2014-05-01)
Luo, Tseng-Chin
;
Chao, Mango C. -T.
;
Tseng, Huan-Chi
;
Goto, Masaharu
;
Fisher, Philip A.
As process technologies continually advance, process variation has greatly increased and has gradually become one of the most critical factors for IC manufacturing. Furthermore, these increasingly complex processes continue to make greater use of stressors for mobility enhancement, thus requiring large volumes of data for extensive characterization of layoutdependent effects (LDE) for validation of both SPICE models and design for manufacturing. Transistor threshold voltage (V-t) is a commonly used parameter both for characterization during process development and for monitoring of volume manufacturing. To adequately quantify local process variation or LDE, V-t must be measured for a sufficiently large number of device-under- tests (DUTs) to obtain a statistically representative sample population. The number of V-t measurements required to obtain such a statistically significant result, however, requires extremely long testing time, especially for array-based test structure designs including thousands of DUTs. In this paper, we present a very fast threshold voltage measurement methodology using an operational amplifier-based source-measure unit test configuration, which greatly improves testing efficiency and accuracy, and is not sensitive to process variation. The proposed test methodology can improve V-t testing time by a factor of 5-10 relative to the commonly used binary-search algorithm, and by a factor of similar to 2 relative to an optimized interpolation algorithm, and achieves better accuracy (standard deviation of V-t = 0.15 mV, versus typical accuracy of similar to 0.5 mV for the two algorithms mentioned). Furthermore, the layout and configuration of conventional test structures need not be modified to adapt the proposed methodology. The measured results from the most advanced process technology nodes demonstrate the testing efficiency and accuracy of the proposed test structure in characterizing the large number of DUTs required for quantifying process variation or LDEs. Index Terms-Design for manufacturing (DFM), Threshold
Fast Transistor Threshold Voltage Measurement Method for High-Speed, High-Accuracy Advanced Process Characterization
(2014-05-01)
Luo, Tseng-Chin
;
Chao, Mango C. -T.
;
Tseng, Huan-Chi
;
Goto, Masaharu
;
Fisher, Philip A.
As process technologies continually advance, process variation has greatly increased and has gradually become one of the most critical factors for IC manufacturing. Furthermore, these increasingly complex processes continue to make greater use of stressors for mobility enhancement, thus requiring large volumes of data for extensive characterization of layoutdependent effects (LDE) for validation of both SPICE models and design for manufacturing. Transistor threshold voltage (V-t) is a commonly used parameter both for characterization during process development and for monitoring of volume manufacturing. To adequately quantify local process variation or LDE, V-t must be measured for a sufficiently large number of device-under- tests (DUTs) to obtain a statistically representative sample population. The number of V-t measurements required to obtain such a statistically significant result, however, requires extremely long testing time, especially for array-based test structure designs including thousands of DUTs. In this paper, we present a very fast threshold voltage measurement methodology using an operational amplifier-based source-measure unit test configuration, which greatly improves testing efficiency and accuracy, and is not sensitive to process variation. The proposed test methodology can improve V-t testing time by a factor of 5-10 relative to the commonly used binary-search algorithm, and by a factor of similar to 2 relative to an optimized interpolation algorithm, and achieves better accuracy (standard deviation of V-t = 0.15 mV, versus typical accuracy of similar to 0.5 mV for the two algorithms mentioned). Furthermore, the layout and configuration of conventional test structures need not be modified to adapt the proposed methodology. The measured results from the most advanced process technology nodes demonstrate the testing efficiency and accuracy of the proposed test structure in characterizing the large number of DUTs required for quantifying process variation or LDEs. Index Terms-Design for manufacturing (DFM), Threshold
Testing Methodology of Embedded DRAMs
(2012-09-01)
Yang, Hao-Yu
;
Chang, Chi-Min
;
Chao, Mango C. -T.
;
Huang, Rei-Fu
;
Lin, Shih-Chin
"The embedded-DRAM(eDRAM) testing mixes up the techniques used for DRAM testing and SRAM testing since an eDRAM core combines DRAM cells with an SRAM interface (the so-called 1T-SRAM architecture). In this paper, we first present our test algorithm for eDRAM testing. A theoretical analysis to the leakage mechanisms of a switch transistor is also provided, based on that we can test the eDRAM at a higher temperature to reduce the total test time and maintain the same retention-fault coverage. Finally, we propose a mathematical model to estimate the defect level caused by wear-out defects under the use of error-correction-code circuitry, which is a special function used in eDRAMs compared to commodity DRAMs. The experimental results are collected based on 1-lot wafers with an 16 Mb eDRAM core."
Testing Methodology of Embedded DRAMs
(2008)
Chang, Chi-Min
;
Chao, Mango C. -T.
;
Huang, Rei-Fu
;
Chen, Ding-Yuan
;
電子工程學系及電子研究所
The embedded-DRAM testing mixes up the techniques used for DRAM testing and SRAM testing since an embedded-DRAM core combines DRAM cells with an SRAM interface (the so-called IT-SRAM architecture). In this paper we first present our test algorithm for embedded-DRAM testing. A theoretical analysis to the leakage mechanisms of a switch transistor is also provided, based on that we can test the embedded-DRAM at a higher temperature to reduce the total test time and maintain the same retention-fault coverage. The experimental results art? collected based on I-lot wafers with an 16Mb embedded DRAM core.