Browsing by Author "Chang, Chia-Jung"

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A 368 x 184 Optical Under-Display Fingerprint Sensor With Global Shutter and High-Dynamic-Range Operation
(2020-01-01)
Yin, Ping-Hung
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Lu, Chih-Wen
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Wang, Jia-Shyang
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Chang, Keng-Li
;
Lin, Fu-Kuo
This study proposes a 368 x 184 optical underdisplay fingerprint sensor designed and prototyped using 0.11-mu m CIS technology. The prototype sensor with global shutter operation and an ADC-embedded in an 8-pixel configuration features low noise, low-power consumption, fast response time, and a smaller signal processing circuit area. Two sets of memory (184 x 92 bytes) are also embedded in the pixel array to save external memory cost. A dynamic range of 126 dB is achieved with 8-segment auto exposure and dark level adjustment with programmable gain control. The prototype fingerprint sensor was successfully embedded in a mobile phone for functional verification, and the power consumption was only 25 mW with a 3.3 V supply voltage. The sensor has a chip size of 9.74 mm x 4.6 mm, a resolution of 1154 dpi, and a sensing area of 73%.
A Novel Cost Effective Double Reduced Surface Field Laterally Diffused Metal Oxide Semiconductor Design for Improving Off-State Breakdown Voltage
(2012-04-01)
Han, Ming-Hung
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Chen, Hung-Bin
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Chang, Chia-Jung
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Wu, Jia-Jiun
;
Chen, Wen-Chong
In this work, double reduced surface field (RESURF) laterally diffused metal oxide semiconductor (LDMOS) device combines a new implant technology without using additional mask in standard 0.18 mu m technology has been proposed and successfully fabricated. The breakdown voltage (BV) can be improved significantly with simply changing the implanted region length in this implant technology. Firstly, hydrodynamic transport simulations which analyze the high bias condition electric field distributions are examined to predict and explain the increase of breakdown voltage. Then the fabricated devices process flow is demonstrated, the structures are performed, and the breakdown voltages increase with different n-type double diffusion (NDD) photoresistor (PR) size using the change of PR exposure dose are investigated. The measurement results show that maximum NDD PR size achieves BV improvement of 6.3%, and 5% increase of figure of merit (FOM) evaluation. Throughout the whole fabrication process, no additional mask and device area show the potential of cost effective with the proposed technique. Such devices with good off-state breakdown voltage and specific on-resistance are very competitive with similar technologies and show good promising in system on chip (SOC) applications. (C) 2012 The Japan Society of Applied Physics
Adaptive Granularity and Coordinated Management for Timely Prefetching in Multi-Core Systems
(2015)
Chang, Chia-Jung
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Peng, Yin-Chi
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Chen, Chien-Chih
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Chen, Tien-Fu
;
Yew, Pen-Chung
For the last decade, there have been varying techniques for hardware prefetching to improve the system performance. However, untimely prefetching may pollution caches and resulting into significant performance degradation. In this work, we introduce an Adaptive Granularity and coordinated Prefetching (AGP) that consists of a coarse-grained and fine-grained prefetched mechanism to provide a better caching environment for parallel applications. AGP targets on the degree-adjusting and location-choosing and tries to minimize the influence caused by prefetcher for each core. AGP could produce more timely prefetched requests reducing the cache pollutions and contentions. Across a variety of PARSEC benchmarks, AGP can contribute 6.5% (up to 36%) of performance improvement on a 4-core multicore system compared to the non-prefetching.
Bidirectional current-mode capacitor multipliers for on-chip compensation
(2008-01-01)
Chen, Ke-Horng
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Chang, Chia-Jung
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Liu, Te-Hsien
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電控工程研究所
;
Institute of Electrical and Control Engineering
Single-ended and two-ended bidirectional capacitor multipliers for providing on-chip compensation, soft-start, and fast transient mechanisms are proposed in this paper. The bidirectional current mode capacitor multiplier technique can effectively move the crossover frequency toward to the origin in the start-up period for a smoothly rising of the output voltage. Besides, the small time constant is set by the fast transient control circuit in order to get a higher crossover frequency. Thus, the output voltage can be regulated to its stable value as fast as it can when large load current changes. A test chip fabricated by the Taiwan Semiconductor Manufacturing Corporation (TSMC) 0.35-mu m process verifies the correctness of the bidirectional current mode capacitor multiplier technique. Experimental results demonstrate the transient speed by our proposed technique is faster than that by conventional. control by about 2 times, and there is only about 76% dropout voltage of the conventional design with off-chip compensation. The proposed circuits consume more quiescent current about 10 mu A in single-ended capacitor multiplier and 20 mu A in two-ended capacitor multiplier. With the proposed bidirectional current mode capacitor multiplier technique, the performance of dc-dc converters is improved significantly and the external pins and footprint area are minimized.
Cross-Layer Dynamic Prefetching Allocation Strategies for High-Performance Multicores
(2013)
Peng, Yin-Chi
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Chen, Chien-Chih
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Chang, Chia-Jung
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Chen, Tien-Fu
;
Yew, Pen-Chung
For the last decade, there have been varying techniques for hardware prefetchers to improve the system performance. However, due to limited space and bandwidth in a multicore system, the prefetching data fetched by prefetcher may pollute L1 cache even though the data is useful, thus resulting into significant performance degradation. Most contemporary multicore systems simply disable prefetching to avoid unexpected contention. This paper proposes a cross-layer and dynamic Prefetch Allocation Management (PAM) to provide better caching strategies in a parallel environment. Our approach has two main mechanisms, targeting at the different prefetch degree and location choices to minimize the cache pollution and contention. Across a variety of SPLASH2 and PARSEC benchmark, our PAM approach can contribute up to 12% of performance improvement on a 4-core multicore system compared to the static prefetcher configuration and also saves 9.1% of the memory bandwidth consumption of memory system.
Cross-Layer Dynamic Prefetching Allocation Strategies for High-Performance Multicores
(2013-01-01)
Peng, Yin-Chi
;
Chen, Chien-Chih
;
Chang, Chia-Jung
;
Chen, Tien-Fu
;
Yew, Pen-Chung
For the last decade, there have been varying techniques for hardware prefetchers to improve the system performance. However, due to limited space and bandwidth in a multicore system, the prefetching data fetched by prefetcher may pollute L1 cache even though the data is useful, thus resulting into significant performance degradation. Most contemporary multicore systems simply disable prefetching to avoid unexpected contention. This paper proposes a cross-layer and dynamic Prefetch Allocation Management (PAM) to provide better caching strategies in a parallel environment. Our approach has two main mechanisms, targeting at the different prefetch degree and location choices to minimize the cache pollution and contention. Across a variety of SPLASH2 and PARSEC benchmark, our PAM approach can contribute up to 12% of performance improvement on a 4-core multicore system compared to the static prefetcher configuration and also saves 9.1% of the memory bandwidth consumption of memory system.
Genome-wide transcriptome analysis to further understand neutrophil activation and lncRNA transcript profiles in Kawasaki disease
(2019-01-23)
Ko, Tai-Ming
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Chang, Jeng-Sheng
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Chen, Shih-Ping
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Liu, Yi-Min
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Chang, Chia-Jung
Kawasaki disease (KD) is the most common cause of acquired cardiac disease in children in developed countries. However, little is known regarding the role of transcriptomic targets of KD in the disease progression and development of complications, especially coronary artery aneurysms (CAA). The aim of our study was to identify transcripts affected by KD and their potential role in the disease. We enrolled 37 KD patients and collected blood samples along a comprehensive time-course. mRNA profiling demonstrated an abundance of CD177 transcript in acute KD, and in the intravenous immunoglobulin (IVIG)-resistant group compared to in the IVIG-sensitive group. lncRNA profiling identified XLOC_006277 as the most highly expressed molecule. XLOC_006277 expression in patients at acute stage was 3.3-fold higher relative to patients with convalescent KD. Moreover, XLOC_006277 abundance increased significantly in patients with CAA. XLOC_006277 knockdown suppressed MMP-8 and MMP-9 expression, both associated with heart lesions. Our result suggested that the increase of CD177(pos) neutrophils was associated with KD. Moreover, this study provided global long non-coding RNA transcripts in the blood of patients with KD, IVIG-resistant KD, or CAA. Notably, XLOC_006277 abundance was associated with CAA, which might contribute to further understanding of CAA pathogenesis in KD.
Improving Breakdown Voltage of LDMOS Using a Novel Cost Effective Design
(2013-05-01)
Han, Ming-Hung
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Chen, Hung-Bin
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Chang, Chia-Jung
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Tsai, Chi-Chong
;
Chang, Chun-Yen
A reduced surface field (RESURF) laterally diffused metal oxide semiconductor (LDMOS) device with the concept of charge compensation using p-implant layer (PIL) without additional process step is proposed in standard 0.18-mu m technology. By simply using the p-type drift drain (PDD) implantation of p-type LDMOS into n-type LDMOS, breakdown voltage (VBD) is substantially improved. For a thorough study of device phenomena, hydrodynamic transport simulations are first performed to analyze the electric field distributions at high voltage bias in order to explain increases in breakdown voltage and predict its optimal design parameter. Then fabrication of the devices is performed and shows that the breakdown voltages increase significantly. The measurement results show a 12% improvement in VBD and a 5% improvement in figure of merit (FOM). Throughout the fabrication process, the enlarged breakdown voltage obtained by the PIL without additional process and device area show the potential of cost effective. Because such devices have good off-state breakdown voltage and specific on-resistance, they are very competitive with similar technologies and promising system-on-chip (SOC) applications.
On-chip compensated error amplifier for fast transient DC-DC converters
(2006)
Huang, Hong-Wei
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Ho, Hsin-Hsin
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Chang, Chia-Jung
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Chen, Ke-Horng
;
Kuo, Sy-Yen
A novel on-chip compensated error amplifier for fast transient response of DC-DC converters is presented in this paper. The error amplifier uses on-chip current-mode Miller capacitor to replace a large off-chip capacitor. We only use three transistors and one voltage follower to implement this novel on-chip compensated error amplifier for fast transient DC-DC converters. Owing to the current-mode implementation, we can redirect the equivalent current to charge or discharge the output capacitor of the error amplifier to improve the transient response time. Not only on-chip compensated error amplifier is implemented without off-chip components and I/O pins, but also it can have fast transient response. The analytic equations guarantee the compensated correctness of the proposed circuit. With the proposed error amplifier, the transient response of DC-DC converters is improved significantly. Simulation results demonstrate the stability and the fast transient response of the DC-DC converters.