Browsing by Author "Chang, Chia-Ling (Lynn)"

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Accurate performance evaluation of VLSI designs with selected CMOS process parameters
(2018-01-01)
Chang, Chia-Ling (Lynn)
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Wen, Charles H. -P.
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電機工程學系
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Department of Electrical and Computer Engineering
As process monitors have become vital components in modern very-large-scale integration (VSLI) designs, performance targets often determine the physical implementation of such monitors. However, as various process and environmental parameters collectively affect circuit behaviour, the design of process monitors can be difficult. In addition, process parameters from device-level models may not provide sufficient resolution in circuit-level performance. Therefore, the authors propose an intelligent novel flow for selecting dominant process parameters for evaluating performance targets such as timing and leakage. The proposed flow is applied to ISCAS'85, ISCAS'89, and IWLS'05 benchmark circuits and selects the dominant parameters in 32 and 45nm complementary metal-oxide-semiconductor (CMOS) technologies. Through this flow, the authors identify the supply voltage, temperature, gate-oxide thickness, and effective gate length as the four dominant factors for timing and leakage. Experimental results show that the suggested process parameters achieve high evaluation accuracy (<3% errors in timing and <1% errors in leakage on average) in the benchmark circuits. Therefore, the proposed flow can select dominant parameters for performance targets, and the four determined factors can be used to accurately evaluate timing and leakage in 32 and 45nm CMOS technologies.
An Intelligent Analysis of Iddq Data for Chip Classification in Very Deep-Submicron (VDSM) CMOS Technology
(2012)
Chang, Chia-Ling (Lynn)
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Chang, Chia-Ching (Austin)
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Chan, Hui-Ling
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Wen, Charles H. -P.
;
Bhadra, Jayanta
Iddq testing has been a critical integral component in test suites for screening unreliable devices. As the silicon technology keeps shrinking, Iddq values and their variation increase as well. Moreover, along with rapid design scaling, defect-induced leakage currents become less significant when compared to full-chip current and also make themselves less distinguishable. Traditional Iddq methods become less effective and cause more test escapes and yield loss. Therefore, in this paper, a new test method named sigma-Iddq testing is proposed and integrates (1) a variation-aware full-chip leakage estimator and (2) a clustering algorithm to classify chip without using threshold values. Experimental result shows that sigma-Iddq testing achieves a higher classification accuracy in a 45nm technology when compared to a single-threshold Iddq testing. As a result, both the process-variation and design-scaling impacts are successfully excluded and thus the defective chips can be identified intelligently.
Demystifying Iddq Data With Process Variation for Automatic Chip Classification
(2015-06-01)
Chang, Chia-Ling (Lynn)
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Wen, Charles H. -P.
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電機資訊學士班
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Undergraduate Honors Program of Electrical Engineering and Computer Science
Iddq testing is an integral component of test suites for the screening of unreliable devices. As the scale of silicon technology continues shrinking, Iddq values and associated fluctuations increase. In addition, increased design complexity makes defect-induced leakage currents difficult to differentiate from full-chip currents. Consequently, traditional Iddq methods result in more test escapes and yield loss. This brief proposes a new test method, called s-Iddq to provide the following: 1) Iddq analysis with process-parameter deduction and 2) the algorithm for automatic chip-classification called collective analysis without the need to manually determine threshold values. We randomly inserted a number of multiple defects into samples of ISCAS\' 89 and IWSL\'05 benchmark circuits. Experimental results demonstrate that the proposed s-Iddq method can achieve higher classification accuracy than single-threshold Iddq testing or sigma-Iddq in a 45-nm technology. The overall classification accuracy of the collective analysis achieve averaged 99.28% and 99.70% on s-Iddq data from process-parameter deductions with average-case search and multilevel search, respectively, demonstrating that the influence of process variation and design scaling can be significantly reduced to enable a better identification of defective chips.
Process-Variation-Aware Iddq Diagnosis for Nano-Scale CMOS Designs - The First Step
(2013-01-01)
Chang, Chia-Ling (Lynn)
;
Wen, Charles H. -P
;
Bhadra, Jayanta
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電機工程學系
;
Department of Electrical and Computer Engineering
Along with the shrinking CMOS process and rapid design scaling, both Iddq values and their variation of chips increase. As a result, the defect leakages become less significant when compared to the full-chip currents, making them more in-distinguishable for traditional Iddq diagnosis. Therefore, in this paper, a new approach called s-Iddq diagnosis is proposed for reinterpreting original data and diagnosing failing chips, intelligently. The overall flow consists of two key components, (1) s-Iddq transformation and (2) defect-syndrome matching: s-Iddq transformation first manifests defect leakages by excluding both the process-variation and design-scaling impacts. Later, defect-syndrome matching applies data mining with a pre-built library to identify types and locations of defects on the fly. Experimental results show that an average of 93.68% accuracy with a resolution of 1.75 defect suspects can be achieved on ISCAS'89 and IWLS'05 benchmark circuits using a 45nm technology, demonstrating the effectiveness of s-Iddq diagnosis.