Browsing by Author "Chang, Chia-Yi"

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Buffer/Flip-Flop Block Planning for Power-Integrity-Driven Floorplanning
(2009)
Pan, Hsin-Hua
;
Chen, Hung-Ming
;
Chang, Chia-Yi
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
As the technology scaled down, it is known that interconnect has become the dominant factor in determining the overall circuit performance and complexity. Buffer insertion is one of very effective and useful techniques to improve the interconnect performance. In order to find better places for buffers to be inserted, the buffer insertion stage during floorplanning usually clusters buffers in a region, which may cause additional IR-drop violation. On the other hand, in complex digital system with relatively large die areas operating at very high frequencies, many global signals traveling across the chip need several clock cycles to reach their destinations, thus requiring the adoption of pipelined interconnects. Together with the buffer stations/blocks, the increasing number of Hip-flops will cause further voltage drop violation. In this paper, we propose a methodology to pipeline interconnect during the floorplan stage and consider the IR-drop during the planning of buffers and flip-flops at the same time. The experimental results show that our method can get a low system latency with power integrity preservation in 90nm technology node.
Design migration from peripheral ASIC design to area-10 flip-chip design by chip I/O planning and legalization
(2006)
Chang, Chia-Yi
;
Chen, Hung-Ming
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Due to higher I/O count and power delivery problem in deep submicron (DSM) regime, flip-chip technology, especially for area-array architecture, has provided more oppertunities for adoption than traditional peripheral bonding design style in high-performance ASIC and microprocessor designs. However it is hard to tell which technique can provide better design cost edge in usually-concerned perspectives. In this paper, we present a methodology to convert a previous peripheral bonding design to an area-IO flip-chip design. It is based on I/O buffer modeling and I/O planning algorithm to legalize I/O buffer blocks with core placement without sacrificing much of the previous optimization in the original core placement. The experimental results have shown that we have acheived better area and I/O wirelength in area-IO flip-chip style, compared with peripheral bonding style in packaging consideration.
Design migration from peripheral ASIC design to area-I/O flip-chip design by chip I/O planning and legalization
(2008-01-01)
Chang, Chia-Yi
;
Chen, Hung-Ming
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Due to higher input/output (I/O) count and power delivery problem in deep submicrometer (DSM) regime, flip-chip technology, especially for area-array architecture, has provided more opportunities for adoption than traditional peripheral bonding design style in high-performance application-specific integrated circuit and microprocessor designs. However, it is hard to tell which technique can provide better design cost edge in usually concerned perspectives. In this paper, we present a methodology to convert a previous peripheral bonding design to an area-I/O flip-chip design. It is based on an I/O buffer modeling and an I/O planning algorithm to legalize I/O buffer blocks with core placement without sacrificing much of the previous optimization in the original core placement. The experimental results have shown that we have achieved better area and I/O wirelength in area-IO flip-chip configuration (especially for pad-limit designs), compared with peripheral bonding configuration in packaging consideration.