Browsing by Author "Chang, Chih-Cheng"

Now showing 1 - 8 of 8

3D Ta/TaOx/TiO2/Ti synaptic array and linearity tuning of weight update for hardware neural network applications
(2016-09-09)
Wang, I-Ting
;
Chang, Chih-Cheng
;
Chiu, Li-Wen
;
Chou, Teyuh
;
Hou, Tuo-Hung
The implementation of highly anticipated hardware neural networks (HNNs) hinges largely on the successful development of a low-power, high-density, and reliable analog electronic synaptic array. In this study, we demonstrate a two-layer Ta/TaOx/TiO2/Ti cross-point synaptic array that emulates the high-density three-dimensional network architecture of human brains. Excellent uniformity and reproducibility among intralayer and interlayer cells were realized. Moreover, at least 50 analog synaptic weight states could be precisely controlled with minimal drifting during a cycling endurance test of 5000 training pulses at an operating voltage of 3 V. We also propose a new state-independent bipolar-pulse-training scheme to improve the linearity of weight updates. The improved linearity considerably enhances the fault tolerance of HNNs, thus improving the training accuracy.
Challenges and Opportunities toward Online Training Acceleration using RRAM-based Hardware Neural Network
(2017-01-01)
Chang, Chih-Cheng
;
Liu, Jen-Chieh
;
Shen, Yu-Lin
;
Chou, Teyuh
;
Chen, Pin-Chun
This paper highlights the feasible routes of using resistive memory (RRAM) for accelerating online training of deep neural networks (DNNs). A high degree of asymmetric nonlinearity in analog RRAMs could be tolerated when weight update algorithms are optimized with reduced training noise. Hybrid-weight Net (HW-Net), a modified multilayer perceptron (MLP) algorithm that utilizes hybrid internal analog and external binary weights is also proposed. Highly accurate online training could be realized using simple binary RRAMs that have already been widely developed as digital memory.
Crossbar array of selector-less TaOx/TiO2 bilayer RRAM
(2015-11-01)
Chou, Chun-Tse
;
Hudec, Boris
;
Hsu, Chung-Wei
;
Lai, Wei-Li
;
Chang, Chih-Cheng
In this work, we have implemented self-rectifying TaOx/TiO2 REAM in a selector-less 6 x 6 crossbar array with various desiring features, including: (1) simple fabrication using only three masks, (2) high self-rectifying ratio up to 10(3) for sneak current suppression, (3) stable bipolar resistive-switching characteristics without the need for electro-forming and current compliance, (4) data retention time over 10(4) s, and (5) robust READ and WRITE disturb immunity. Finally, an achievable array size of 1 Mb was simulated using an All-LPU read scheme and a V/3 write scheme. (C) 2015 Elsevier Ltd. All rights reserved.
Design of a Novel Flexible Capacitive Sensing Mattress for Monitoring Sleeping Respiratory
(2014-11-01)
Chang, Wen-Ying
;
Huang, Chien-Chun
;
Chen, Chi-Chun
;
Chang, Chih-Cheng
;
Yang, Chin-Lung
In this paper, an algorithm to extract respiration signals using a flexible projected capacitive sensing mattress (FPCSM) designed for personal health assessment is proposed. Unlike the interfaces of conventional measurement systems for poly-somnography (PSG) and other alternative contemporary systems, the proposed FPCSM uses projected capacitive sensing capability that is not worn or attached to the body. The FPCSM is composed of a multi-electrode sensor array that can not only observe gestures and motion behaviors, but also enables the FPCSM to function as a respiration monitor during sleep using the proposed approach. To improve long-term monitoring when body movement is possible, the FPCSM enables the selection of data from the sensing array, and the FPCSM methodology selects the electrodes with the optimal signals after the application of a channel reduction algorithm that counts the reversals in the capacitive sensing signals as a quality indicator. The simple algorithm is implemented in the time domain. The FPCSM system is used in experimental tests and is simultaneously compared with a commercial PSG system for verification. Multiple synchronous measurements are performed from different locations of body contact, and parallel data sets are collected. The experimental comparison yields a correlation coefficient of 0.88 between FPCSM and PSG, demonstrating the feasibility of the system design.
Development of Three-Dimensional Synaptic Device and Neuromorphic Computing Hardware
(2016-01-01)
Wang, I-Ting
;
Chou, Teyuh
;
Chiu, Li-Wen
;
Chang, Chih-Cheng
;
Hou, Tuo-Hung
To facilitate the development of low-cost, low-power, and high-density hardware neural networks, we have successfully developed a Ta/TaOx/TiO2/Ti RRAM-based synaptic device. The device exhibits numerous synaptic functions resembling those in biological synapses, including synaptic plasticity of potentiation and depression, spike-timing dependent plasticity, paired-pulse facilitation and a transition from short-term to long-term memory. We further demonstrate 3D high-density, high-connectivity integration of the Ta/TaOx/TiO2/Ti device, and the device exhibits excellent uniformity among interlayer and intralayer cells in a 4 x 4 3D two-layer cross-point array. Finally, we investigate the influence of nonlinearity of synaptic weight updates on neuromorphic computing. A state-independent training scheme is proposed to improve linearity and fault tolerance of training accuracy.
Extremely Compact Integrate-and-Fire STT-MRAM Neuron: A Pathway toward All-Spin Artificial Deep Neural Network
(2019-01-01)
Wu, Ming-Hung
;
Hong, Ming-Chun
;
Chang, Chih-Cheng
;
Sahu, Paritosh
;
Wei, Jeng-Hua
This work reports the complete framework from device to architecture for deep learning acceleration in an all-spin artificial neural network (ANN) built by highly manufacturable STT-MRAM technology. The most compact analog integrate-and-fire neuron reported to date is developed based on the back-hopping oscillation in magnetic tunnel junctions. This novel device is unique because it performs numerous essential neural functions simultaneously, including current integration, voltage spike generation, state reset, and 4-bit precision. The device itself is also a stochastic binary synapse, and thus eases the implementation of the compact all-spin ANN with high accuracy for online training.
Mitigating Asymmetric Nonlinear Weight Update Effects in Hardware Neural Network Based on Analog Resistive Synapse
(2018-03-01)
Chang, Chih-Cheng
;
Chen, Pin-Chun
;
Chou, Teyuh
;
Wang, I-Ting
;
Hudec, Boris
Asymmetric nonlinear weight update is considered as one of the major obstacles for realizing hardware neural networks based on analog resistive synapses, because it significantly compromises the online training capability. This paper provides new solutions to this critical issue through co-optimization with the hardware-applicable deep-learning algorithms. New insights on engineering activation functions and a threshold weight update scheme effectively suppress the undesirable training noise induced by inaccurate weight update. We successfully trained a two-layer perceptron network online and improved the classification accuracy of MNIST handwritten digit data set to 87.8%/94.8% by using 6-/8-b analog synapses, respectively, with extremely high asymmetric nonlinearity.
Sub-nA Low-Current HZO Ferroelectric Tunnel Junction for High-Performance and Accurate Deep Learning Acceleration
(2019-01-01)
Wu, Tzu-Yun
;
Huang, Hsin-Hui
;
Chu, Yueh-Hua
;
Chang, Chih-Cheng
;
Wu, Ming -Hung
This paper presents a unique opportunity of HZO ferroelectric tunnel junction (FTJ) for in-memory computing. The device operates at an extremely low sub-nA current while simultaneously achieving 50-ns fast switching, > 10(7) cycling endurance, > 10-yr retention, minimal variability, and analog state modulation. We analyze an FTJ-based deep binary neural network. It achieves better accuracy and remarkable 702, 101, and 7 x 10(4) times improvements in power, area, and energy area product efficiency compared with those using NVMs with a typical mu A cell current designed for fast memory access.