Browsing by Author "Chang, Chih-Long"

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INTEGRA: Fast Multi-Bit Flip-Flop Clustering for Clock Power Saving Based on Interval Graphs
(2011)
Jiang, Iris H. -R.
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Chang, Chih-Long
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Yang, Yu-Ming
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Tsai, Evan Y. -W.
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Chen, Lancer S. -F.
Clock power is the major contributor to dynamic power for modern IC design. A conventional single-bit; flip-flop cell uses an inverter chain with a high drive strength to drive the clock signal. Clustering such cells and forming a multi-bit flip-flop can share the drive strength, dynamic power, and area of the inverter chain, even can save the clock network power and facilitate the skew control. Hence, in this paper, we focus on multi-bit flip-flop clustering at post-placement to gain these benefits. Utilizing the properties of Manhattan distance and coordinate transformation, we model the problem instance by two interval graphs and use a pair of linear-size sequences as our representation. Without enumerating all compatible combinations, we extract only partial sequences that are necessary to cluster flip-flops at a time, thus leading to an efficient clustering scheme. Moreover, our coordinate transformation brings fast; operations to execute our algorithm. Experimental results show the superior efficiency and effectiveness of our algorithm.
INTEGRA: Fast Multibit Flip-Flop Clustering for Clock Power Saving
(2012-02-01)
Jiang, Iris Hui-Ru
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Chang, Chih-Long
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Yang, Yu-Ming
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Clock power is the major contributor to dynamic power for modern integrated circuit design. A conventional single-bit flip-flop cell uses an inverter chain with a high drive strength to drive the clock signal. Clustering several such cells and forming a multibit flip-flop can share the drive strength, dynamic power, and area of the inverter chain, and can even save the clock network power and facilitate the skew control. Hence, in this paper, we focus on postplacement multibit flip-flop clustering to gain these benefits. Utilizing the properties of Manhattan distance and coordinate transformation, we model the problem instance by two interval graphs and use a pair of linear-sized sequences as our representation. Without enumerating all possible combinations, we identify only partial sequences that are necessary to cluster flip-flops, thus leading to an efficient clustering scheme. Moreover, our fast coordinate transformation also makes the execution of our algorithm very efficient. The experiments are conducted on industrial circuits. Our results show that concise representation delivers superior efficiency and effectiveness. Even under timing and placement density constraints, clock power saving via multibit flip-flop clustering can still be substantial at postplacement.
Novel Pulsed-Latch Replacement Based on Time Borrowing and Spiral Clustering
(2012)
Chang, Chih-Long
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Jiang, Iris Hui-Ru
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Yang, Yu-Ming
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Tsai, Evan Yu-Wen
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Chen, Aki Sheng-Hua
Flip-flops are the most common form of sequencing elements; however, they have a significantly higher sequencing overhead than latches in terms of delay, power, and area. Hence, pulsed-latches are promising to reduce power for high performance circuits. In this paper, we propose a novel pulsed-latch replacement approach to save power and satisfy timing constraints. We fully utilize the intrinsic time borrowing property of pulsed-latches and develop a spiral clustering method with clock gating consideration. In addition, spiral clustering works well for both rectangular and rectilinear shaped layouts; the latter are popular in modern IC design. Experimental results show that our approach can generate very power efficient results.
Pulsed-Latch Replacement Using Concurrent Time Borrowing and Clock Gating
(2013-02-01)
Chang, Chih-Long
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Jiang, Iris Hui-Ru
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Flip-flops are the most common form of sequencing elements; however, they have a significantly higher sequencing overhead than latches in terms of delay, power, and area. Hence, pulsed latches are a promising option to reduce power for high-performance circuits. In this paper, to save power and compensate for timing violations, we fully utilize the intrinsic time borrowing property of pulsed latches and consider clock gating during pulsed-latch replacement. Experimental results show that our approach can generate very power efficient results.
WiT: Optimal Wiring Topology for Electromigration Avoidance
(2012-04-01)
Jiang, Iris Hui-Ru
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Chang, Hua-Yu
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Chang, Chih-Long
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Due to excessive current densities, electromigration (EM) may trigger a permanent open- or short-circuit failure in signal wires or power networks in analog or mixed-signal circuits. As the feature size keeps shrinking, this effect becomes a key reliability concern. Hence, in this paper, we focus on wiring topology generation for avoiding EM at the routing stage. Prior works tended towards heuristics; on the contrary, we first claim this problem belongs to class P instead of class NP-hard. Our breakthrough is, via the proof of the greedy-choice property, we successfully model this problem on a multi-source multi-sink flow network and then solve it by a strongly polynomial time algorithm. Experimental results prove the effectiveness and efficiency of our algorithm.